Sundance SMT784 v.1.0 - Manual (Page 13)

Version 1.0 Page 13 of 31 SMT784 User Manual
The SMT784 connects 8 lanes to the PXIe connector, 4 lanes to an RSL connector,
two lanes to Fibre Modules, and two lanes to front panel SATA connectors.
For FPGAs with only 12 GTPs (high speed serial ports), no lanes are available on the
RSL connector.
Future releases of the firmware will allow for Host application access of the RSL link.
Flash
This 64Mbyte memory contains the configuration bit-stream for the FPGA.
The flash contents may be programmed via the PXIe/PCI interface or via USB by
using the SMT6002.
CPLD and FPGA Configuration
This Xilinx CPLD is capable of configuring the FPGA using data provided from the
flash memory. The CPLD itself should not need to be re-programmed, but if needed it
can only be accessed by JTAG using Xilinx iMPACT.
The CPLD also interfaces to a Cypress USB device. This interface allows an easy
option for upgrading the FPGA configuration stored in flash using the SMT6002.
The USB mechanism to re-program the flash is always present and does not rely on
the FPGA being configured. This can be advantageous if the FPGA configuration has
been updated with a non-working PCI interface.
SHB
Two Sundance SHB connectors are fitted as standard. Each connector has the ability
to carry a 32-bit data bus with a data rate of 133MHz. A dual 16-bit interface option is
also supported.
One SHB is connected directly to the FPGA. To save on pin-count, the second SHB
connector shares the PCI interface signals with the FPGA. For this reason, this SHB
interface and the PCI cannot be operated simultaneously unless a PCI express core
is implemented in firmware.
LEDs
Two front-panel LED’s are available and connected directly to the FPGA. A heartbeat
signal present indicates the FPGA has been configured correctly.