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4 core modifications, Core modifications – Sundance FC100 User Manual

Page 8

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4.3.4 Core modifications

The standard IP Core is available in netlist or parameterized source code and supports the
following:

 Netlist builds for any Xilinx FPGA device

o

FFT length and speed depend on chip resources and speed grade

 Per-transform length selectable in powers-of-2

o

from 32 to 2

m

points, where m= 5-26

 Per-transform mode selectable between Forward and Inverse FFT

 Static length and mode configuration

o

Pipeline must be clear before changing these configuration settings.

 IEEE-754 single precision floating point math operators using Xilinx Coregen

o

full DSP usage/maximum latency floating_point_v4_0 cores

 Decimation-in-time (DIT) algorithm with internal bit-reversal

o

providing natural-order data inputs and outputs

Potential customized deliveries from Dillon Engineering include:

 Fixed single length of 2

m

for a slight logic

o

savings over run-time selectable length.

 Fixed Forward or Inverse mode for a slight logic

o

savings over run-time selectable mode.

 Pipelined configuration settings

o

allows dynamic mode and/or length switching on back-to-back transforms.

 Bit-reversal stage removed for a slight logic savings and elimination of a

BlockRAM FIFO and associated latency.

o

Note: data must then be input in bit-reversed order to provide natural-

order outputs

 Decimation-in-frequency (DIF) build option, which inputs data in natural-order

and outputs data in bit-reversed order.

 Any Xilinx Floating Point operator adjustments to precision and latencies, with

logic parameter settings to match. Xilinx Floating Point operators are built
separately with Coregen, providing RTL source and .ngc netlists. Thus all trade-
offs between speed, number of pipeline stages, DSP48/Mult macro usage, double-
or custom-precision float, etc., can be supported.

 Any width fixed-point math operators in lieu of floating point. Options for various

scaling, rounding and saturation modes, all matched bit-accurate with the C/C++-
model.

User Manual FC100

Page 8 of 12

Last Edited: 25/11/2008 15:00:00