Dell R510 - Manual (Page 45)

Dell
PowerEdge R510 Technical Guide 45
8.2.3 PCI Express* Interfaces
PCI Express* Interfaces include:
•
Intel 5500 chipset IOH provides multiple PCI Express* Gen 2 interfaces
•
Point-to-point, serial bi-directional interconnect
• One x4 ESI link to ICH10
•
Up to six x4 PCI Express Gen 2 ports
•
x4 link pairs can be combined to form x8 links and or x16 links
•
Each signal is 8b/10b encoded with an embedded clock
• Signaling bit rate of 5 Gbit/sec/lane/direction; for an x4 link, bandwidth is 2 GB/sec in each
direction
•
Hot Insertion and Removal supported with the addition of Hot-Plug control circuitry
8.2.4 SMBus Interfaces
• Connected globally to CPUs, IOHs, and ICH through a common shared bus hierarchy.
• Low pin count, low speed management interface
•
Provides access to configuration status registers (CSR’s)
•
Mastered by the baseboard management controller (BMC)
8.2.5 ESI interface
The ESI interface connects the Intel 5500 chipset MCH to the ICH10R. The ESI interface runs at 2 GB/s with a
100 MHz reference clock.
8.3 Intel ICH10R South Bridge
The PowerEdge R510 planar incorporates the Intel ICH10R chip. The ICH10R is a highly integrated I/O
controller.
8.3.1 DMI interface
The DMI interface connects the ICH10R to the IOH. The DMI interface runs at 2 GB/s with a 100 MHz
reference clock.
8.3.2 SATA interface
The ICH10R contains 6 integrated Serial ATA host controllers capable of independent DMA operation on 6
ports.
The ICH10R SATA interface supports data transfers up to 300 MB/s. The ICH10R has an integrated AHCI
controller.
8.3.3 USB interface
The ICH10R is USB 2.0 compliant. It has six UHCI host controllers to support twelve ports and two EHCI host
controller to support twelve ports. An over-current condition can be detected on all twelve ports.
8.3.4 PCI Express interface
The ICH10R has 6 PCI Express 1.1 compliant root ports.