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Appendix e – DFI CD952 series User Manual

Page 64

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64

Appendix E Digital I/O User Guide

Appendix E

4.2 Control of GP80 to GP87

#define AddrPort 0x2E
#define DataPort 0x2F


WriteByte(AddrPort, 0x87)
WriteByte(AddrPort, 0x87) //Must write twice to entering
Extended mode


WriteByte(AddrPort, 0x07)
WriteByte(AddrPort, 0x06)
//Select logic device 06h

//SetGPIO71/72 to output Mode
WriteByte(AddrPort, 0x80)// Select configuration register 80h
WriteByte(DataPort, (ReadByte(DataPort)

ǀ 0x06))

//Set (bit 0/1) = (1) to select GPIO 71/72 as Output mode.


WriteByte(AddrPort, 0x81)// Select configuration register 81h
WriteByte(DataPort, Value)// Set bit n=(1/2) to output GPI07n
as Low or High


WriteByte(AddrPort, 0xAA)