External interface headers jp1, jp2, and jp4 – Zilog Z16F2810 User Manual
Page 15
ZNEO
®
Z16F Series Development Kit
User Manual
UM020205-0908
ZNEO Z16F Series Development Board
11
External Interface Headers JP1, JP2, and JP4
External interface headers JP1, JP2, and JP4 are provided in
J3
IN
IrDA interface
disabled.
X
J6
OUT
8-bit MDS interface
disabled.
X
J6
IN
8-bit MDS interface
enabled.
J7
OUT
External Flash Write Protect disabled.
X
J7
IN
External Flash Write Protect enabled.
Note: * These jumpers must not be OUT at the same time.
Table 2. ZNEO Jumper Settings (Continued)
Jumper
Status
Function
Default