ADLINK cExpress-BT - Manual (Page 16)

Page 16 cExpress-BT
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A81 LVDS_A_CK+ * B81 LVDS_B_CK+ * C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK- * B82 LVDS_B_CK- * C82 PEG_RX9- D82 PEG_TX9-
A83 LVDS_I2C_CK * B83 LVDS_BKLT_CTRL * C83 TPM_PP D83 RSVD
A84 LVDS_I2C_DAT * B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10-
A87 RSVD B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11-
A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 TPM_PP B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 RSVD
A98 SER0_TX / CAN_TX B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 SER0_RX / CAN_RX B99 RSVD C99 PEG_RX14- D99 PEG_TX14-
A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 SER1_TX B101 FAN_PWMOUT C101 PEG_RX15+ D101 PEG_TX15+
A102 SER1_RX B102 FAN_TACHIN C102 PEG_RX15- D102 PEG_TX15-
A103 LID# ** B103 SLEEP# ** C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
Notes:
- LID# and SLEEP# signals are not natively supported on the SOC. They instead connect to GPIO pins simulating their behaviour.
- LVDS can be supported by build option that reoutes DDI1 to a eDP to LVDS bridge.
- PCIe (port 3) can be supported by BOM option (lose GbE).