ADLINK PXIS-2690P - Manual (Page 18)

10 Chassis Overview
System Reference Clock
The PXIS-2690P supplies a 10 MHz system reference clock signal
(PXI_CLK10) to every peripheral slot independently. An indepen-
dent buffer (having a source impedance matched to the backplane
and a skew of less than 1 ns between slots) drives the clock signal
to each peripheral slot. You can use this common reference clock
signal to synchronize multiple modules in a measurement or con-
trol system, or drive PXI_CLK10 from an external source through
the PXI_CLK10_IN pin on the P2 connector of the star trigger slot.
You can select the internal or external clock by setting jumpers
JP2 and JP3 in the backplane rear. Refer to the jumper settings
below.
Description Jumper Settings
External clock (PXI_CLK10_IN
on star trigger slot)
JP2 Open
JP3 Short
Internal clock (10 MHz system
clock PXI_CLK10)
JP2 Short
JP3 Open
Table 2-1: Reference Clock Jumper Setting