Acrosser AR-B1661 - Manual (Page 27)

AR-B1661 Manual
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3.5 ADVANCED CHIPSET FEATURES
This Setup menu controls the configuration of the motherboard chipset.
Auto Configuration
This field predefines values for DRAM, cache timing according to CPU type and system clock. When this field is
enabled, the predefined items will become read-only.
SDRAM RAS-to-CAS Delay
When DRAM is refreshed, both rows and columns are addressed separately. This field allows you to determine
the timing of transition from Row Address Strove (RAS) to Column Address Strobe (CAS). The default setting is
3
.
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to accumulate its charge before DRAM
refreshes. If insufficient time is allowed, refresh may be incomplete and the DRAM may fail to retain data. The
default setting is 3.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing.
Do not reset this field from the default value specified by the system designer. The default setting is 3.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at F0000H-FFFFFH is cached, provided that the
cache controller is disabled.