Acrosser AR-B1320 - Manual (Page 9)

A A R R - - B B 1 1 3 3 2 2 0 0 U U s s e e r r ’ ’ s s G G u u i i d d e e
2-1
2. SYSTEM CONTROLLER
This chapter describes the major structure. The following topics are covered:
l Microprocessor
l DMA Controller
l DRAM Configuration
l I/O Port Address Map
l Interrupt Controller
l Serial Port
l Parallel Port
l Timer
l Real-Time Clock and Non-Volatile RAM
l Watch-Dog Timer
l FLASH Disk
2.1 MICROPROCESSOR
The AR-B1320 uses the ALI M6117C CPU; it is designed to perform like Intel’ s 386SX-based
system with deep green features.
The 386SX core is the same as M1386SX of Acer Labs. Inc. and 100% object code compatible
with the Intel 386SX microprocessor. System manufacturers can provide 386 CPU based
systems optimized for both cost and size. Instruction pipelining and high bus bandwidth ensure
short average instruction-execution times and high system throughput. Furthermore, it can keep
the state internally from charge leakage while external clock to the core is stopped without storing
the data in registers. The power consumption here is almost zero when the clock stops. The
internal structure of this core is 32-bit and it’ s address bus has a very low supply current. The real
mode as well as the protected mode are available and can run MS-DOS, MS-Windows, OS/2 and
UNIX.
2.2 DMA CONTROLLER
The equivalent of two 8237A DMA controllers are implemented in the AR-B1320 card. Each
controller is a four-channel DMA device, which will generate the memory addresses and control
signals necessary to transfer information directly between a peripheral device and memory. This
allows high-speed information transfer with less CPU intervention. The two DMA controllers are
internally cascaded to provide four DMA channels for transfers to 8-bit peripherals (DMA1) and
three channels for transfers to 16-bit peripherals (DMA2). DMA2 channel 0 provides the cascade
interconnection between the two DMA devices, thereby maintaining the IBM PC/AT compatibility.
The following is the DMA channels:
DMA Controller 1 DMA Controller 2
Channel 0: Spare Channel 4: Cascade for controller 1
Channel 1: IBM SDLC Channel 5: Spare
Channel 2: Diskette adapter Channel 6: Spare
Channel 3: Spare Channel 7: Spare
Table 2-1 DMA Channel Controller