Kontron CP3-BP4-M - Manual (Page 4)

PD02: CP3-BP4-M CPCI Backplane
Page 4 © 2002 PEP Modular Computers GmbH RID 24229 PD02, Rev. 01
3. Board Layout
Figure 1: CP3-BP4-M Board Layout (Front and Reverse Side)
4. Signalling Environment
4.1 V(I/O) Setting
The backplane provides a block of three high-current terminals (designated as V(I/O)) for con-
necting V(I/O) to either the +5V or +3.3V power supply. V(I/O) must be connected either to the
+5V or the +3.3V input power. It is the responsibility of the system integrator to ensure that the
required signalling voltage is implemented and that the backplane P1 connector coding corre-
sponds to the implemented signalling voltage.
Warning!
Using both 3.3V and 5V boards within the same system may result in
damage to your equipment. Please note that the presence of only one
5V board determines a 5V signalling environment. The default setting
is 5V.
4 3 2 1 2 4 3 1
JP2 JP1
+3.3V VIO +5V
GND GND