Kontron ADD2-LVDS-DUAL-Internal - Manual (Page 8)

ADD2-LVDS
KTD-00711-D Public User Manual Date: 2008-09-16 Page 8 of 13
LVDS Flat Panel Connector J1 and J2.
Connector type is Don Connex C44-40-B-G-1. Mating connector can be Don Connex A32-40-C-G-B-1
(Kontron item no.
910000005).
The J1 and J2 connector are identical, but J2 is only available on the ADD2-LVDS-Dual version.
Note Type Signal Pin Signal Type Note
Max. 0.5A PWR +12V 1 2 +12V PWR Max. 0.5A
Max. 0.5A PWR +12V 3 4 +12V PWR Max. 0.5A
Max. 0.5A PWR +12V 5 6 GND PWR Max. 0.5A
Max. 0.5A PWR +3.3V 7 8 GND PWR Max. 0.5A
Max. 0.5A PWR LCDVCC 9 10 LCDVCC PWR Max. 0.5A
5K6Ω, LCDVCC OT DDC CLK 11 12 DDC DATA OT 5K6Ω, LCDVCC
110RΩ, 3.3V PWR 3.3V signal 13 14 VDD ENABLE OT 3.3V level
3.3V level OT BKLTEN# 15 16 GND PWR Max. 0.5A
LVDS LVDS A0- 17 18 LVDS A0+ LVDS
LVDS LVDS A1- 19 20 LVDS A1+ LVDS
LVDS LVDS A2- 21 22 LVDS A2+ LVDS
LVDS LVDS ACLK- 23 24 LVDS ACLK+ LVDS
LVDS LVDS A3- 25 26 LVDS A3+ LVDS
Max. 0.5A PWR GND 27 28 GND PWR Max. 0.5A
LVDS LVDS B0- 29 30 LVDS B0+ LVDS
LVDS LVDS B1- 31 32 LVDS B1+ LVDS
LVDS LVDS B2- 33 34 LVDS B2+ LVDS
LVDS LVDS BCLK- 35 36 LVDS BCLK+ LVDS
LVDS LVDS B3- 37 38 LVDS B3+ LVDS
Max. 0.5A PWR GND 39 40 GND PWR Max. 0.5A
Signal Description – LVDS Flat Panel Connector:
Signal Description
LVDS A0..A3 LVDS A Channel data
LVDS ACLK LVDS A Channel clock
LVDS B0..B3 LVDS B Channel data
LVDS BCLK LVDS B Channel clock
3.3V Signal 100Ω to 3.3V. Can be used to generate 0-3.3V by potentiometer etc. for backlight
intensity control.
BKLTEN# Backlight Enable signal, Active Low (~GND) as default. Use DIP-SW3/4 to select Active
High (~3.3V).
VDD ENABLE Output Display Enable. Active High (~3.3V).
LCDVCC VCC supply to the flat panel. This supply includes power-on/off sequencing.
The flat panel supply may be either 3.3V (default) or 5V depending on the DIP-SW1/2. If
5V is requested then PWR connector must be used. Maximum load is 1A.
DDC CLK DDC Channel Clock. Pull-up resistor to LCDVCC.
DDC DATA DDC Channel Data. Pull-up resistor to LCDVCC.