MSI IM-GS45-M User Manual

Page 56

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SYSTEM RESOURCES

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POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS

pre-boot process. The following table describes the type of checkpoints that may

occur during the POST portion of the BIOS:

Checkpoint

Description

Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS,

POST, Runtime data area. Also initialize BIOS modules on POST entry

and GPNV area. Initialized CMOS as mentioned in the Kernel Variable

“wCMOSFlags.”

Check CMOS diagnostic byte to determine if battery power is OK and

CMOS checksum is OK. Verify CMOS checksum manually by reading

storage area. If the CMOS checksum is bad, update CMOS with power-on

default values and clear passwords. Initialize status register A. Initializes

data variables that are based on CMOS setup questions. Initializes both

the 8259 compatible PICs in the system

Initializes the interrupt controlling hardware (generally PIC) and interrupt

vector table.

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the

POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt.

Traps INT1Ch vector to “POSTINT1ChHandlerBlock.”

Initializes the CPU. The BAT test is being done on KBC. Program the

keyboard controller command byte is being done after Auto detection of

KB/MS using AMI KB-5.

Initializes the 8042 compatible Key Board Controller.

Detects the presence of PS/2 mouse.

Detects the presence of Keyboard in KBC port.

Testing and initialization of different Input Devices. Also, update the Ker-

nel Variables. Traps the INT09h vector, so that the POST INT09h handler

gets control for IRQ1. Uncompress all available language, BIOS logo, and

Silent logo modules.