MSI 880G-E45 - Manual (Page 63)

3-23
MS-7576
Chapter 3
tRAS
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. This setting determines the time RAS takes to read from and write to a memory
cell.
tRTP
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. This setting controls the time interval between a read and a precharge com-
mand.
tRC
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. The row cycle time determines the minimum number of clock cycles a memory
row takes to complete a full cycle, from row activation up to the precharging of the
active row.
tWR
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. It specifies the amount of delay (in clock cycles) that must elapse after the
completion of a valid write operation, before an active bank can be precharged. This
delay is required to guarantee that data in the write buffers can be written to the
memory cells before precharge occurs.
tRRD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. Specifies the active-to-active delay of different banks.
tWTR
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the field is adjust-
able. This item controls the Write Data In to Read Command Delay memory timing.
This constitutes the minimum number of clock cycles that must occur between the
last valid write operation and the next read command to the same internal bank of
the DDR device.
tRFC0~3
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these fields are
adjustable. These settings determine the time RFC take to read from and write to
memory cells.
tWRTTO
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these fields
are adjustable. Timing of Read to Write turnaround for data; the minimum cycle
time between command last clock of CAS read operation to next command write
operation. If you set this item smaller, system will run faster but might be more
unstable. Please set it depends on memory module.
tWRRD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these fields are
adjustable. Timing of Write to Read; the minimum cycle time from last clock of first
virtual CAS write-burst operation to a following one read-burst operation for different
chip or DIMM.If you set this item smaller, system will run faster but might be more
unstable.Please set it depends on memory module.
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