Analog Devices MicroConverter ADuC824 User Manual

Page 2

(not used)

(reserved)

7Fh

...

30h

2Fh

2Eh

2Dh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22h

21h

20h

1Fh

1Eh

1Dh

1Ch

1Bh

1Ah

19h

18h

17h

16h

15h

14h

13h

12h

11h

10h

0Fh

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

07h

06h

05h

04h

03h

02h

01h

00h

General Purpose

Area

Bit Addressable

Area

Bank 3

Bank 2

Bank 1

Bank 0

7Fh

7Eh

7Dh

7Ch

7Bh

7Ah

79h

78h

77h

76h

75h

74h

73h

72h

71h

70h

6Fh

6Eh

6Dh

6Ch

6Bh

6Ah

69h

68h

67h

66h

65h

64h

63h

62h

61h

60h

5Fh

5Eh

5Dh

5Ch

5Bh

5Ah

59h

58h

57h

56h

55h

54h

53h

52h

51h

50h

4Fh

4Eh

4Dh

4Ch

4Bh

4Ah

49h

48h

47h

46h

45h

44h

43h

42h

41h

40h

3Fh

3Eh

3Dh

3Ch

3Bh

3Ah

39h

38h

37h

36h

35h

34h

33h

32h

31h

30h

2Fh

2Eh

2Dh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22g

21h

20h

1Fh

1Eh

1Dh

1Ch

1Bh

1Ah

19h

18h

17h

16h

15h

14h

13h

12h

11g

10h

0Fh

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

07h

06h

05h

04h

03h

02h

01h

00h

127

...

decimal

address

HEX

address

(bit addresses)

SFRs

(direct

addressing

only)

128 bytes

upper RAM

(indirect

addressing

only)

128 bytes

lower RAM

(direct or

indirect

addressing)

640 bytes

(160 pages)

data

Flash/EE

(accessible

through

SFRs)

external

data

memory

(16MEG

addressable)

SFR details

lower RAM

details

SPICON

F8h

04h

F0h

00h

DCON

E8h

00h

ACC

E0h

00h

ADCST

D8h

00h

PSW

D0h

00h

T2CON

C8h

00h

WDCON

C0h

10h

B8h

00h

B0h

FFh

A8h

00h

A0h

FFh

SCON

98h

00h

90h

FFh

TCON

88h

00h

80h

FFh

ADC0L

D9h

00h

ECON

B9h

00h

IEIP2

A9h

A0h

SBUF

99h

00h

TMOD

89h

00h

81h

07h

ADC0M

DAh

00h

ADC0CON

D2h

07h

RCAP2L

CAh

00h

TL0

8Ah

00h

DPL

82h

00h

DACL

FBh

00h

ADC1CON

D3h

00h

RCAP2H

CBh

00h

TL1

8Bh

00h

DPH

83h

00h

DACH

FCh

00h

D4h

45h

TL2

CCh

00h

EDA

BCh

00h

TH0

8Ch

00h

DPP

84h

00h

DACCON

FDh

00h

TH2

CDh

00h

EDA

BDh

00h

TH1

8Dh

00h

EADRL

C6h

00h

EDA

BEh

00h

SPIDA

F7h

00h

PSMCON

DFh

DEh

EDA

BFh

00h

PCON

87h

00h

SPR0

F8h

F0h

E8h

E0h

D8h

D0h

CAP2

C8h

WDWR

C0h

PX0

B8h

RXD

B0h

EX0

A8h

A0h

98h

90h

IT0

88h

80h

SPR1

F9h

F1h

E9h

E1h

D9h

D1h

CNT2

C9h

WDE

C1h

PT0

B9h

TXD

B1h

ET0

A9h

A1h

99h

T2EX

91h

IE0

89h

81h

CPHA

F2h

EAh

E2h

ERR1

DAh

D2h

TR2

CAh

WDS

C2h

PX1

BAh

INT0

B2h

EX1

AAh

A2h

RB8

9Ah

92h

IT1

8Ah

82h

CPOL

FBh

F3h

D0EN

EBh

E3h

ERR0

DBh

RS0

D3h

EXEN2

CBh

WDIR

C3h

PT1

BBh

INT1

B3h

ET1

ABh

A3h

TB8

9Bh

93h

IE1

8Bh

83h

SPIM

FCh

F4h

ECh

E4h

NOXREF

DCh

RS1

D4h

TCLK

CCh

PRE0

C4h

BCh

B4h

ACh

A4h

REN

9Ch

94h

TR0

8Ch

84h

SPE

FDh

F5h

EDh

E5h

CAL

DDh

D5h

RCLK

CDh

PRE1

C5h

PT2

BDh

B5h

ET2

ADh

A5h

SM2

9Dh

95h

TF0

8Dh

85h

WCOL

FEh

F6h

D1EN

EEh

E6h

RDY1

DEh

D6h

EXF2

CEh

PRE2

C6h

ADC

BEh

B6h

EADC

AEh

A6h

SM1

9Eh

96h

TR1

8Eh

86h

ISPI

FFh

F7h

EFh

E7h

RDY0

DFh

D7h

TF2

CFh

PRE3

C7h

BFh

B7h

AFh

A7h

SM0

9Fh

97h

TF1

8Fh

87h

MSB

address

LSB

address

00h

000000h

FFFFFFh

FFh

9Fh

00h

( page 0 )

( page 159 )

SPR0

F8h

SPICON

F8h

00h

SPR1

F9h

mnemonic

reset value
address

mnemonic

address

reset value

these bits

this byte

are contained in

calibration coefficients are preconfigured at power-up to factory calibrated values

ADC0H

DBh

00h

ADC1L

DCh

00h

ADC1H

DDh

00h

ICON

D5h

00h

ADCMODE

D1h

00h

GN0L

E9h

~55h

GN0M

EAh

~55h

OF0M

E2h

00h

OF0H

E3h

80h

OF1L

E4h

00h

GN0H

EBh

~53h

GN1L

ECh

~9Ah

GN1H

EDh

~59h

OF1H

E5h

80h

OF0L

E1h

00h

PLLCON

D7h

03h

CHIPID

C2h

06h

TIMECON

A1h

00h

HTHSEC

A2h

00h

SEC

A3h

00h

MIN

A4h

00h

HOUR

A5h

00h

INTV

A6h

00h

DACCON.4

DAC pin select bit [0=pin3 / 1=pin12]

DACCON.3

ModeSelect (0=12bit, 1=8bit)

DACCON.2

RangeSelect (0=2.5V, 1=AV

)

DACCON.1

Clear DAC (0=0V, 1=normal operation)

DACCON.0

PowerDown DAC (0=off, 1=on)

ISPI

SPI inturrupt (set at end of SPI transfer)

WCOL

write collision error flag

SPE

SPI enable (0=DCON enable, 1=SPI enable)

SPIM

master mode select (0=slave)

CPOL

clock polarity select (0=SCLK idles low)

CPHA

clock phase select (0=leading edge latch)

SPR1

SPI bitrate select bits

SPR0

bitrate = F

CORE

/ [2, 4, 8, 16]

AD0CON.7

(this bit must contain zero)

AD0CON.6

external reference select bit (0=internal ref)

AD0CON.5

channel selection bits:

AD0CON.4

[AIN1-AIN2,AIN3-AIN4,AIN2-AIN2,AIN3-AIN2]

AD0CON.3

unipolar select bit (0=bipolar)

AD0CON.2

range select bits:

AD0CON.1

[±20mV, ±40mV, ±80mV, ±160mV, ±320mV,

AD0CON.0

±640mV, ±1.28V, ±2.56V]

RDY0

primary ADC ready flag

RDY1

auxiliary ADC ready flag

CAL

calibration flag

NOXREF

no external reference flag

ERR0

primary ADC error flag

ERR1

auxiliary ADC error flag

DACCON

DAC Control register

Sync Filter Register: f

ADC

= 4,096Hz ÷ (3·SF)

SPICON

SPI Control register

SPIDAT

SPI Data register

ADC0CON

Primary ADC Control Register

auxiliary math register

ADCSTAT

ADC Status Register

ACC

Accumulator

PSMCON

Power Supply Monitor control register

PSMCON.7

compare bit (0=fault)

PSMCON.6

compare bit (0=fault)

PSMCON.5

PSM interrupt bit

PSMCON.4

trip point select bits

PSMCON.3

[4.63V, 3.08V, 2.93V, 2.63V]

PSMCON.2

trip point select bits

PSMCON.1

[4.63V, 3.08V, 2.93V, 2.63V]

PSMCON.0

PSM powerdown control (1=on / 0=off)

ADCMODE

ADC Mode Register

ADMODE.5

primary ADC enable bit

ADMODE.4

auxiliary ADC enable bit

ADMODE.2

mode bits

ADMODE.1

[powerdown, idle, sngl-conv, cont-conv,

ADMODE.0

zero-selfcal, fs-selfcal, zero-syscal, fs-syscal]

ADC1CON

Auxiliary ADC Control Register

carry flag

auxiliary carry flag

general purpose flag 0

RS1

RS0

active register bank = [0,1,2,3]

overflow flag

general purpose flag 1

parity of ACC

DACH

DACL

DAC data registers

PSW

Program Status Word

TH2,TL2

Timer2 register

RCAP2H,RCAP2L

Timer2 Reload/Capture

TF2

overflow flag

EXF2

external flag

RCLK

receive clock enable (0=Timer1 used for RxD clk)

TCLK

transmit clock enable (0=Timer1 used for TxD clk)

EXEN2

external enable (0=ignore T2EX, 1=cap/rld on T2EX)

TR2

run control (0=stop, 1=run)

CNT2

timer/counter select (0=timer, 1=counter)

CAP2

capture/reload select (0=reload, 1=capture)

T2CON

Timer2 Control register

EADRH

EADRL

Data Flash/EE address registers

PRE3

watchdog timeout selection bits

PRE2

0000-0111 = timeout=[15.6, 31.2, 62.5, 125, 500

PRE1

1000 = immediate reset

1000, 2000] ms

PRE0

all others codes = reserved

WDIR

watchdog interrupt response enable

WDS

watchdog status flag

WDE

watchdog enable

WDWR

watchdog write enable

WDCON

Watchdog Timer control register

EDATA1

EDATA2

EDATA3

EDATA4

Data Flash/EE data registers

01h READ page
02h PROGRAM page
04h VERIFY page
05h ERASE page
06h ERASE ALL

ECON

Data Flash/EE comand register

IP.7

(not used)

PADC

priority of RDY0/RDY1 (ADC interrupt)

PT2

priority of TF2/EXF2 (Timer2 overflow interrupt)

priority of RI/TI (serial port interrupt)

PT1

priority of TF1 (Timer1 overflow interrupt)

PX1

priority of IE1 (external INT1)

PT0

priority of TF0 (Timer0 overflow interrupt)

PX0

priority of IE0 (external INT0)

Interrupt Priority register

external data memory read strobe

external data memory write strobe

timer/counter 1 external input

timer/counter 0 external input

INT1

external interrupt 1

INT0

external interrupt 0

TxD

serial port transmit data line

RxD

serial port receive data line

Port3 register

IEIP2.7

(not used)

IEIP2.6

pirority of TII interrupt (timer interval)

IEIP2.5

priority of PSMI interrupt (power supply monitor)

IEIP2.4

priority of ISPI interrupt (serial interface)

IEIP2.3

(this bit must contain zero)

IEIP2.2

enable TII interrupt (timer interval)

IEIP2.1

enable PSMI interrupt (power supply monitor)

IEIP2.0

enable ISPI interrupt (serial interface)

IEIP2

Interrupt Enable/Priority register #2

enable inturrupts (0=all inturrupts disabled)

EADC

enable RDY0/RDY1 (ADC interrupt)

ET2

enable TF2/EXF2 (Timer2 overflow interrupt)

enable RI/TI (serial port interrupt)

ET1

enable TF1 (Timer1 overflow interrupt)

EX1

enable IE1 (external interrupt 1)

ET0

enable TF0 (Timer0 overflow interrupt)

EX0

enable IE0 (external interrupt 0)

Interrupt Enable register #1

Port2 register

SBUF

Serial port Buffer register

SM0

UART mode control bits

baud rate:

SM1

00 - 8bit shift register - F

CORE

/12

01 - 8bit UART

- TimerOverflowRate/32(x2)

10 - 9bit UART

- F

CORE

/64(x2)

11 - 9bit UART

- TimerOverflowRate/32(x2)

SM2

in modes 2&3, enables multiprocessor communication

REN

receive enable control bit

TB8

in modes 2&3, 9th bit transmitted

RB8

in modes 2&3, 9th bit received

transmit interrupt flag

receive interrupt flag

SCON

Serial communications Control register

P1.2-1.7 analog/digital pins (1=analog function, 0=digital input)
T2EX

timer/counter 2 capture/reload trigger (or digital I/O)

timer/counter 2 external input (or digital I/O)

Port1 register

TH0,TL0

Timer0 registers

TH1,TL1

Timer1 registers

TMOD.3/.7

gate control bit (0=ignore INTx)

TMOD.2/.6

counter/timer select bit (0=timer)

TMOD.1/.5

timer mode selecton bits

TMOD.0/.4

[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]

(upper nibble = Timer1, lower nibble = Timer0)

TMOD

Timer Mode register

TF1

Timer1 overflow flag

TR1

Timer1 run control (0=off, 1=run)

TF0

Timer0 overflow flag

TR0

Timer0 run control (0=off, 1=run)

IE1

external INT1 flag

IT1

IE1 type (0=level trig, 1=edge trig)

IE0

external INT0 flag

IT0

IE0 type (0=level trig, 1=edge trig)

TCON

Timer Control register

PCON.7 double baud rate control
PCON.6 enable serial interrupt (ISI) from power-down mode
PCON.5 enable interrupt 0 (INT0) from power-down mode
PCON.4 ALE disable (0=normal, 1=forces ALE high)
PCON.3 general purpose flag
PCON.2 general purpose flag
PCON.1 power-down control bit (0=normal)
PCON.0 idle-mode control (0=normal)

PCON

Power Control register

DPP

Data Pointer Page

DPH,DPL (DPTR)

Data Pointer

Stack Pointer

Port0 register

81h READ byte
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)

AD1CON.6

external reference select bit (0=internal ref)

AD1CON.5

channel selection bits:

AD1CON.4

[AIN3, AIN4, TEMP, AIN5]

AD1CON.3

unipolar select bit (0 = bipolar)

ICON.6

burnout current enable bit

ICON.5

ADC1 current correction bit (0=correction off)

ICON.4

ADC0 current correction bit (0=correction off)

ICON.3

I2 pin select bit [0=pin4 / 1=pin3]

ICON.2

I1 pin select bit [0=pin3 / 1=pin4]

ICON.1

I2 enable bit (0=disable)

ICON.0

I1 enable bit (0=disable)

ICON

Current Source Control Register

PLLCON.7

oscillator powerdown control bit (0=normal)

PLLCON.6

PLL lock indicator flag (0=out of lock)

PLLCON.5

(this bit must contain zero)

PLLCON.4

EA detect status bit (reflects state of EA pin)

PLLCON.3

“fast interrupt” control bit (0=normal)

PLLCON.2

3-bit clock divideer value, “CD” (default=3):

PLLCON.1
PLLCON.0

PLLCON

PLL Control Register

CORE

= 12,582,912Hz ÷ 2

CHIPID

Chip ID Register

(0X hex = ADuC824)

TIMECON.6 24hour select bit (0=255hour)
TIMECON.5 interval timebase select bits
TIMECON.4 [128th sec, seconds, minutes, hours]
TIMECON.3 single time interval control bit (0=reload&restart)
TIMECON.2 time interval interrupt bit, “TII”
TIMECON.1 time interval enable bit (0=disable&clear)
TIMECON.0 time clock enable bit (0=disable)

TIMECON

Time Interval Counter Control Register

HTHSEC

TIC Elapsed 128th Second Register

SEC

TIC Elapsed Seconds Register

MIN

TIC Elapsed Minutes Register

HOUR

TIC Elapsed Hours Register

INTVAL

TIC Interval Register

OF0H

OF0M

OF0L

ADC0 offset coefficient

OF1H

OF1L

ADC1 offset coefficient

GN0H

GN0M

GN0L

ADC0 gain coefficient

GN1H

GN1L

ADC1 gain coefficient

ADC0H

ADC0M

ADC0L

ADC0 data

ADC1H

ADC1L

ADC1 data

(enabled if SPE=0, see SPICON register above)

D1 output bit

D1EN

D1 output enable (0=disable)

D0 output bit

D0EN

D0 output enable (0=disable)

DCON

D0 & D1 Control register

SFR MAP & RESET VALUES

SFR DESCRIPTIONS

DATA MEMORY SPACE

(read/write area)

LOWER RAM

DATA MEMORY:

RAM, SFRs, user Flash/EE (all read/write)

MAP KEY