AMD ATHLON 8 User Manual
Page 103
Appendix B - Conventions and Abbreviations
91
25175H—March 2003
AMD Athlon™ XP Processor Model 8 Data Sheet
Preliminary Information
IDE
Integrated Device Electronics
ISA
Industry Standard Architecture
IPC
Instructions Per Cycle
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LAN
Large Area Network
LRU
Least-Recently Used
LVTTL
Low Voltage Transistor Transistor Logic
MSB
Most Significant Bit
MTRR
Memory Type and Range Registers
MUX
Multiplexer
NMI
Non-Maskable Interrupt
OD
Open-Drain
OPGA
Organic Pin Grid Array
PA
Physical Address
PBGA
Plastic Ball Grid Array
PCI
Peripheral Component Interconnect
PDE
Page Directory Entry
PDT
Page Directory Table
PGA
Pin Grid Array
PLL
Phase Locked Loop
PMSM
Power Management State Machine
POS
Power-On Suspend
POST
Power-On Self-Test
PP
Push-Pull
RAM
Random Access Memory
ROM
Read Only Memory
RXA
Read Acknowledge Queue
SCSI
Small Computer System Interface
SDI
System DRAM Interface
SDRAM
Synchronous Direct Random Access Memory
SIMD
Single Instruction Multiple Data
SIP
Serial Initialization Packet
SMbus
System Management Bus
Table 32. Acronyms (continued)
Abbreviation
Meaning