6 chipset, North bridge chipset configuration, Execute disable bit [enabled – Asus P5B User Manual
Page 95: Hyper threading technology [enabled, Peci [disabled, Inter(r) speedstep (tm) tech. [disabled, Configuration options: [disabled] [enabled, Configuration options: [disabled] [automatic
![6 chipset, North bridge chipset configuration, Execute disable bit [enabled | Hyper threading technology [enabled, Peci [disabled, Inter(r) speedstep (tm) tech. [disabled, Configuration options: [disabled] [enabled, Configuration options: [disabled] [automatic | Asus P5B User Manual | Page 95 / 188](/screens/49083/95.png)
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