Teledyne LeCroy QPHY-HDMI - Manual (Page 25)

QPHY-HDMI Operator’s Manual
Test7-9: TMDS Clock Jitter
This test confirms that the TMDS Clock does not carry excessive jitter.
R EQUIREMENT
TMDS differential clock jitter must not exceed 0.25*TBIT, relative to the ideal Recovery Clock.
Reference: [HDMI: Table 4-16] Source AC Characteristics at TP1
T EST M ETHODOLOGY
1. Connect TPA-P adapter to the Source DUT HDMI output connector.
2. Connect two TF-HDMI-3.3V test fixtures to each line of the TMDS Clock pair.
3. Configure oscilloscope and CRU: evaluate 16M samples per channel (can be acquired
with a single or with multiple smaller captures).
4. Configure Source DUT to output one video format for each of the following TMDS Clock
frequencies if that frequency is supported by the DUT: 27MHz (or 25MHz), 74.25MHz,
148.5MHz, and 222.75MHz. For each of these test frequencies, perform the following:
a. Capture the waveform and process it with the Digital Oscilloscope.
b.
If test frequency is <=165MHz, then set Sampling Rate ≥10GSa/s
If test frequency is >165MHz, then set Sampling Rate ≥20GSa/s
c. Measure Clock jitter as difference between farthest left sampling point and
farthest right sampling point, at Vertical setting = VC = 0V ± 20mV. If Clock jitter
exceeds 0.25*TBIT then FAIL.
5. Repeat the test for remaining supported test frequencies. Only one video format/pixel-
size combination is required per TMDS clock rate.
922540 Rev A 21