beautypg.com

AAEON HSB-CV1P User Manual

Page 89

background image

H a l f - s i z e S B C

H S B - C V 1 P

Appendix A Programming the Watchdog Timer A-2

A.1 Programming

HSB-CV1P utilizes FINTEK 81866 chipset as its watchdog timer

controller. Below are the procedures to complete its configuration

and the AAEON initial watchdog timer program is also

attached based on which you can develop customized

program to fit your application.

Configuring Sequence Description

After the hardware reset or power-on reset, the FINTEK 81866

enters the normal mode with all logical devices disabled

except KBC. The initial state (enable bit ) of this logical device

(KBC) is determined by the state of pin 121 (DTR1#) at the falling

edge of the system reset during power-on reset.