Rainbow Electronics MAX1446 - Manual (Page 12)

MAX1446
10-Bit, 60Msps, +3.0V, Low-Power
ADC with Internal Reference
12 ______________________________________________________________________________________
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal refer-
ence provides a V
DD
/2 output voltage for level shifting
purposes. The input is buffered and then split to a volt-
age follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associ-
ated with high-speed op amps. The user may select the
R ISO and C IN values to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an R
ISO of 50 Ω is placed before the capaci-
tive load to prevent ringing and oscillation. The 22pF
C
IN capacitor acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1446 for
optimum performance. Connecting the transformer’s
center tap to COM provides a V
DD /2 DC level shift to
80
70
60
50
40
20 40 30 50 60 70
CLOCK DUTY CYCLE (%)
SFDR (dBc)
f IN = 12.5MHz AT -0.5dBFS
Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input)
40
50
45
60
55
65
70
20 40 30 50 60 70
CLOCK DUTY CYCLE (%)
SNR (dB)
f
IN
= 12.5MHz AT -0.5dBFS
Figure 3b. SNR vs. Clock Duty Cycle (Differential Input)
-40
-50
-60
-70
-80
20 40 30 50 60 70
CLOCK DUTY CYCLE (%)
THD (dBc)
f IN = 12.5MHz AT -0.5dBFS
Figure 4a. THD vs. Clock Duty Cycle (Differential Input)
40
50
45
60
55
65
70
20 40 30 50 60 70
CLOCK DUTY CYCLE (%)
SINAD (dB)
f IN = 12.5MHz AT -0.5dBFS
Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input)