Rainbow Electronics MAX1205 - Manual (Page 8)

MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
8 _______________________________________________________________________________________
Requirements for Reference
and Analog Signal Inputs
Fully differential switched-capacitor circuits (SC) are
used for both the reference and analog inputs (Figure 2).
This allows either single-ended or differential signals to
be used in the reference and/or analog signal paths.
The signal voltage on these pins (INP, INN, RFN_,
RFP_) should never exceed the analog supply rail,
AV
DD , and should not fall below ground.
Choice of Reference
It is important to choose a low-noise reference, such as
the MAX6341, which can provide both excellent load
regulation and low temperature drift. The equivalent
input circuit for the reference pins is shown in Figure 3.
Note that the reference pins drive approximately 1k
Ω
of
resistance on chip. They also drive a switched capaci-
tor of 21pF. To meet the dynamic performance, the ref-
erence voltage is required to settle to 0.0015% within
one clock cycle. Accomplish this by choosing an
appropriate driving circuit (Figure 4). The capacitors at
the reference pins (RFPF, RFNF) provide the dynamic
charge required during each clock cycle, while the op
amps ensure accuracy of the reference signals. These
capacitors must have low dielectric-absorption charac-
teristics, such as polystyrene or teflon capacitors.
The reference pins can be connected to either single-
ended or differential voltages within the specified maxi-
mum levels. Typically the positive reference pin (RFPF)
would be driven to 4.096V, and the negative reference
pin (RFNF) connected to analog ground. There are
sense pins, RFPS and RFNS, which can be used with
RFPF
INP
INN
RFPF
CM
CM
RFNF
Figure 2. Simplified MDAC Architecture
RFPF
RFPS
RFNF
RFNS
Figure 3. Equivalent Input at the Reference Pins. The sense
pins should not draw any DC current.
STAGE1
7
DAV
INP
CM AV DD RFN_ RFP_ AGND
INN
CLK
DV
DD
DGND
DRV DD
ST_CAL
DOR D13–D0
17
ADC
ADC MDAC
8X S/H
STAGE2 STAGE3 STAGE4
CORRECTION AND
CALIBRATION LOGIC END_CAL
OE
OUTPUT DRIVERS
CLOCK
GENERATOR
MAX1205
Figure 1. Internal Block Diagram