Rainbow Electronics MAX782 - Manual (Page 16)

MAX782
Triple-Output Power-Supply
Controller for Notebook Computers
16 ______________________________________________________________________________________
+5V Transformer (T1)
Table 3 lists two commercially available transformers
and parts for a custom transformer. The following
instructions show how to determine the transformer
parameters required for a custom design:
L
P
, the primary inductance value
I
LPEAK
, the peak primary current
LI 2 , the core’s energy rating
R
P
and R
S
, the primary and secondary resistances
N, the primary-to-secondary turns ratio.
The transformer primary is specified just as the +3.3V
inductor, using V
OUT
= +5.0V; but the secondary output
(VDD) power must be added in as if it were part of the
primary. VDD current (I
DD
) usually includes the VPPA
and VPPB output currents. The total +5V power, P
TOTAL
,
is the sum of these powers:
P
TOTAL
= P5 + P
DD
where: P5 = V
OUT
x I
OUT
;
P
DD
= VDD x I
DD
;
and: V
OUT
= output voltage, 5V;
I
OUT
= maximum +5V load current (A);
VDD = VDD output voltage, 15V;
I
DD
= maximum VDD load current (A);
so: P
TOTAL
= (5V x I
OUT
) + (15V x I
DD
)
and the equivalent +5V output current, I
TOTAL
, is:
I
TOTAL
= P
TOTAL
/ 5V
= [(5V x I
OUT
) + (15V x I
DD
)] / 5V.
The primary inductance, L
P
, is given by:
V
OUT
x (V
IN(MAX)
- V
OUT
)
L P = ———————————————
V
IN(MAX)
x f x I
TOTAL
x LIR
where: V
OUT
= output voltage, 5V;
V
IN(MAX)
= maximum input voltage;
f = switching frequency, normally 300kHz;
I
TOTAL
= maximum equivalent load current (A);
LIR = ratio of primary peak-to-peak AC
current to average DC load current, typically 0.3.
The highest peak primary current (I
LPEAK
) equals the
total DC load current (I
TOTAL
) plus half the peak-to-peak
AC primary current (I
LPP
). The peak-to-peak AC primary
current is typically chosen as 30% of the maximum DC
load current, so the peak primary current is 1.15 times
I
TOTAL
. A higher value of LIR allows smaller inductance,
but results in higher losses and higher ripple.
The peak current in the primary at full load is given by:
V
OUT
x (V
IN(MAX
) - V
OUT
)
I
LPEAK
= I
TOTAL
+ —————————————.
2 x f x L P x V
IN(MAX)
Choose a core with an LI 2 parameter greater than L
P
x
I
LPEAK
2 .
The winding resistances, R
P
and R
S
, should be as low
as possible, preferably in the low milliohms. Use the
largest gauge wire that will fit on the core. The coil is
effectively in series with the load at all times, so the
resistive losses in the primary winding alone are
approximately (I
TOTAL
) 2 x R
P
.
The minimum turns ratio, N
MIN
, is 5V:(15V-5V). Use 1:2.2
to accommodate the tolerance of the +5V supply. A
greater ratio will reduce efficiency of the VPP regulators.
Minimize the diode capacitance and the interwinding
capacitance, since they create losses through the
VDD shunt regulator. These are most significant when
the input voltage is high, the +5V load is heavy, and
there is no load on VDD.
Ensure the transformer secondary is connected with the
right polarity: A VDD supply will be generated with either
polarity, but proper operation is possible only with the cor-
rect polarity. Test for correct connection by measuring the
VDD voltage when VDD is unloaded and the input voltage
(V
IN
) is varied over its full range. Correct connection is
indicated if VDD is maintained between 13V and 20V.
Current-Sense Resistors (R1, R2)
The sense resistors must carry the peak current in the
inductor, which exceeds the full DC load current.
The internal current limiting starts when the voltage
across the sense resistors exceeds 100mV nominally,
80mV minimum. Use the minimum value to ensure
adequate output current capability: For the +3.3V
supply, R1 = 80mV / (1.15 x I
OUT
); for the +5V supply,
R2 = 80mV/(1.15 x I
TOTAL
), assuming that LIR = 0.3.
Since the sense resistance values (e.g. R1 = 25m
Ω
for
I
OUT
= 3A) are similar to a few centimeters of narrow
traces on a printed circuit board, trace resistance can
contribute significant errors. To prevent this, Kelvin
connect the CS_ and FB_ pins to the sense resistors;
i.e., use separate traces not carrying any of the induc-
tor or load current, as shown in Figure 5.
Run these traces parallel at minimum spacing from one
another. The wiring layout for these traces is critical for
stable, low-ripple outputs (see the
Layout and
Grounding section).
MOSFET Switches (N1-N4)
The four N-channel power MOSFETs are usually iden-
tical and must be “logic-level” FETs; that is, they must
be fully on (have low r
DS(ON)
) with only 4V gate-
source drive voltage. The MOSFET r
DS(ON)
should
ideally be about twice the value of the sense resistor.
MOSFETs with even lower r
DS(ON)
have higher gate
capacitance, which increases switching time and
transition losses.