Rainbow Electronics MAX1243 User Manual

Page 11

If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser-
ial clock. Choose a clock frequency up to 2.1MHz.

1) Use a general-purpose I/O line on the CPU to pull CS

low. Keep SCLK low.

2) Wait the maximum conversion time specified before

activating SCLK. Alternatively, look for a DOUT rising
edge to determine the end of conversion.

3) Activate SCLK for a minimum of 11 clock cycles. The

first falling clock edge produces the MSB of the
DOUT conversion. DOUT output data transitions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK-to-DOUT valid timing char-
acteristic. Data can be clocked into the µP on
SCLK’s rising edge.

4) Pull CS high at or after the 11th falling clock edge. If

CS remains low, the two sub-bits and trailing zeros
are clocked out after the LSB.

5) With CS = high, wait the minimum specified time, t

before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion’s end, wait the minimum acquisition
time, t

ACQ

, before starting a new conversion.

Data can be output in two bytes or continuously, as
shown in Figures 8a and 8b. The bytes contain the
result of the conversion padded with one leading 1, two
sub-bits, and trailing 0s if SCLK is still active with CS
kept low.

SPI and Microwire

When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion is in progress. Wait until
DOUT goes high or until the maximum specified 7.5µs
conversion time elapses. Two consecutive 1-byte reads
are required to get the full 10+2 bits from the ADC.
DOUT output data transitions on SCLK’s falling edge
and is clocked into the µP on SCLK’s rising edge.

The first byte contains a leading 1, and seven bits of
conversion result. The second byte contains the remain-
ing three bits, two sub-bits, and three trailing zeros. See
Figure 11 for connections and Figure 12 for timing.

QSPI

Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 10 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
sary to clock in the data. The MAX1242/MAX1243 require
11 clock cycles from the µP to clock out the 10 bits of
data. Additional clock cycles clock out the two sub-bits
followed by trailing zeros (Figure 13). The maximum clock
frequency to ensure compatibility with QSPI is 2.097MHz.

Layout and Grounding

For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

______________________________________________________________________________________

HIGH-Z

CONV

DOUT

SCLK

1ST BYTE READ

2ND BYTE READ

EOC

MSB

LSB

HIGH-Z

CONV

DOUT

SCLK

EOC

MSB

LSB

Figure 12. SPI/Microwire Serial-Interface Timing (CPOL = CPHA = 0)

Figure 13. QSPI Serial-Interface Timing (CPOL = CPHA = 0)