Rainbow Electronics DS2705 - Manual (Page 12)

DS2705: SHA-1 Authentication Master
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Table 5. Configuration Register
FIELD NAME DESCRIPTION DEFAULT
CR[1:0] RTA1:0
Re-Tries Per Authentication Attempt
Each re-try includes:
OWR, PD, Skip ROM, Write Challenge, Read MAC, Compare MAC, Final OWR/PD
0 0 0 Re-try (1 attempt per initiation)
0 1 1 Re-tries (2 attempts per initiation)
1 0 3 Re-tries (4 attempts per initiation)
1 1 7 Re-tries (8 attempts per initiation)
PASS output hi-Z until authentication complete.
Authentication complete after first occurrence of a PASS result or all re-tries are a FAIL result
00b
CR[3:2] PAA1:0
Periodic Authentication Attempt
Each Attempt performed with the programmed number of re-tries:
0 0 No Periodic Attempts
0 1 Attempt every 1s
1 0 Attempt every 8s
1 1 Attempt every 16s
PASS and FAIL pins retain previous states until updated when authentication completed. If
presence not detected, status outputs are cleared to hi-Z.
00b
CR[5:4] PPT1:0
Periodic Presence Test
1-Wire Presence test performed at programmed period:
0 0 No Periodic Test
0 1 Attempt every 0.25s
1 0 Attempt every 0.5s
1 1 Attempt every 1.0s
PASS and FAIL pins retain previous states if presence detected. PASS and FAIL pins are cleared to
hi-Z and status flags are cleared to zero if presence not detected.
00b
CR[6] APA
Asynchronous Presence Authentication
0 No
1 Yes
Authentication sequence initiated t
CHD
ms delay after Presence Detect from token.
0b
CR[7] CHP
CHAL Pin Polarity Setting
0 High to low transition; active low
1 Low to high transition; active high
0b
CR[8] FOM
FAIL Output Select
0 FAIL pin held low
1 FAIL pin pulsed low at 2Hz 50% duty cycle
0b
CR[9] OWS
1-Wire Bus Speed
0 Standard 1-wire communication (Master and Slave)
1 Overdrive 1-wire communication (Master and Slave)
0b
CR[11:10] LOCK1:0
EEPROM Lock
0 0 No Operation
0 1 No Operation
1 0 Permanently Lock EEPROM
1 1 No Operation
Writing a 10b to the lock bits, followed by an EEPROM copy will permanently lock all EEPROM
locations inside the DS2705. Writing any other value to the lock bits will perform no operation.
00b
CR[12] ¾ RESERVED 0b
CR[13] FAILF
FAIL flag. Mirrors the FAIL pin output for test via slave interface (SDQ pin). Set if authentication
attempt fails. Cleared when subsequent authentication attempt initiated.
0b
CR[14] PASSF
PASS flag. Mirrors the PASS pin output for test via slave interface (SDQ pin). Set if authentication
attempt passes. Cleared when subsequent authentication attempt initiated.
0b
CR[15] LOCKF Displays Lock/Unlock Status. LOCKF = 1 if lock procedure successful. 0b