Rainbow Electronics AT89LV55 - Manual (Page 13)

AT89LV55
13
Power Down Mode
In the power down mode, the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before V
CC
is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Program Memory Lock Bits
The AT89LV55 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table:
Lock Bit Protection Modes
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
The AT89LV55 code memory array is programmed byte-
by-byte. To program any non-blank byte in the on-chip
Flash Memory, the entire memory must be erased using
the Chip Erase Mode.
Programming the Flash
The AT89LV55 is normally shipped with the on-chip Flash
memory array in the erased state (that is, contents = FFH)
and ready to be programmed.
Programming Algorithm: Before programming the
AT89LV55, the address, data and control signals should be
set up according to the Flash programming mode table and
Figure 9 and Figure 10. To program the AT89LV55, take
the following steps:
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V
PP
to 12V
5. Pulse ALE/PROG once to program a byte in the Flash
array or the lock bits. The byte-write cycle is self-timed
and typically takes no more than 1.5 ms. Repeat steps
1 through 5, changing the address and data for the
entire array or until the end of the object file is reached.
Data Polling: The AT89LV55 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on PO.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BUSY output signal. P3.4 is
pulled low after ALE goes high during programming to indi-
cate BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features.
2 P U U MOVC instructions executed from external program memory are disabled from fetching code
bytes from internal memory, EA is sampled and latched on reset, and further programming of
the Flash memory is disabled.
3 P P U Same as mode 2, but verify is also disabled.
4 P P P Same as mode 3, but external execution is also disabled.