Rainbow Electronics DS1673 - Manual (Page 7)

DS1673
7 of 18
STATUS REGISTER
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CU LOBAT 0 0 0 0 0 IRQF
CU (Conversion Update In Progress) - When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488
µs. When this bit is a 0, an update to the ADC Register will not occur for at
least 244 µs.
LOBAT (Low Battery Flag) - This bit reflects the status of the backup power source connected to the
V
BAT
pin. When V
BAT
is greater than 2.5 volts, LOBAT is set to a logic 0. When V
BAT
is less than
2.3 volts, LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up: EOSC , TD1 and TD0. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1673 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the V
CCO
pin. The DS1673 was specifically designed with the Intel 80186 and 386EX microprocessors in mind.
As such, the DS1673 has the capability to provide access to the external SRAM in either byte-wide or
word-wide format. This capability is provided by the chip enable scheme. Three input signals and two
output signals are used for enabling the external SRAM(s) (see Figure 4).
CEI (chip enable in), BHE
(byte high enable), and BLE (byte low enable) are used for enabling either one or two external SRAMs
through the CEOL (chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the
function of these pins.
The DS1673 nonvolatilizes the external SRAM(s) by write-protecting the SRAM(s) and by providing a
back-up power supply in the absence of V
CC
. When V
CC
falls below V
PF
, access to the external SRAM(s)
are prohibited by forcing CEOL and CEOH high regardless of the level of CEI , BLE , and BHE . Upon
power-up, access is prohibited until the end of t
RPU
.
EXTERNAL SRAM CHIP ENABLE Table 3
CEI BHE BLE CEOL CEOH
FUNCTION
0 0 0 0 0 Word transfer
0 0 1 1 0 Byte transfer in upper half of data bus (D15-D8)
0 1 0 0 1 Byte transfer in lower half of data bus (D7-D0)
0 1 1 1 1 External SRAMs disabled
1 X X 1 1 External SRAMs disabled