Rainbow Electronics DS1286 - Manual (Page 12)

DS1286
12 of 13
NOTES:
1. WE is high for a read cycle.
2. OE = V
IH
or V
IL
. If OE = V IH during write cycle, the output buffers remain in a high impedance
state.
3. t
WP
is specified as the logical AND of the CE and WE . t
WP
is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. t
DS
or t
DH
are measured from the earlier of CE or WE going high.
5. t
DH
is measured from WE going high. If CE is used to terminate the write cycle, then t
DH
= 20 ns.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write
Cycle 1, the output buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9. Each DS1286 is marked with a four-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected t
DR
is defined as starting at the date of
manufacture.
10. All voltages are referenced to ground.
11. Applies to both interrupt pins when the alarms are set to pulse.
12. Interrupt output occurs within 100 ns on the alarm condition existing.
13. Both INTA and INTB (INTB) are open drain outputs.
14. Real-Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns.