Rainbow Electronics MAX5953D - Manual (Page 17)

The two-switch power topology recovers energy stored
in both the magnetizing and the parasitic leakage induc-
tances of the transformer. The Typical Application
Circuit, Figure 3, shows the schematic diagram of a -48V
input flyback converter using the MAX5953A. Figure 4
shows the schematic diagram of a -48V input forward
converter and a 5V, 3A output isolated power supply.
Voltage-Mode Control and the PWM Ramp
For voltage-mode control, the feed-forward PWM ramp
is generated at RCFF. From RCFF, connect a capacitor
to GND and a resistor to HVIN. The ramp generated is
applied to the noninverting input of the PWM compara-
tor at RAMP and has a minimum voltage of approxi-
mately 2V. The slope of the ramp is determined by the
voltage at HVIN and affects the overall loop gain. The
ramp peak must remain below the 5.5V dynamic range
of RCFF. Assuming the maximum duty cycle approach-
es 50% at a minimum input voltage (PWM UVLO turn-
on threshold), use the following formula to calculate the
minimum value of either the ramp capacitor or resistor:
where f S is the switching frequency, V R(P-P) is the peak-
to-peak ramp voltage (2V, typ). Select R
RCFF
resistance
value between 200k Ω and 600kΩ.
Maximize the signal-to-noise ratio by setting the ramp
peak as high as possible. Calculate the low-frequency,
small-signal gain of the power stage (the gain from the
inverting input of the PWM comparator to the output)
using the following formula:
G PS = N SP x R RCFF x C RCFF x f S
where N SP is the secondary to primary power trans-
former turns ratio.
Secondary-Side Synchronization
The MAX5953A/MAX5953B/MAX5953C/MAX5953D
provide convenient synchronization for optional sec-
ondary-side synchronous rectifiers. Figure 5 shows the
connection diagram with a high-speed optocoupler.
Choose an optocoupler with a propagation delay of
less than 80ns. The synchronizing pulse is generated
approximately 110ns ahead of the main pulse that dri-
ves the two power MOSFETs.
Undervoltage Lockout for DC-DC Converter
Connect PGOOD to DCUVLO to ensure the PD interface
is ready prior to the DC-DC converter. The DCUVLO
block monitors the input voltage at HVIN through an
external resistive divider (R16 and R17) connected to
DCUVLO (see Figure 3). Use the following equation to
calculate R16 and R17:
where V
DCUVLOIN
is the desired input voltage lockout
level and V
DCUVLO
is the undervoltage lockout thresh-
old (1.25V, typ). Select the R17 resistance value
between 100k
Ω and 500kΩ.
Optocoupled Feedback
Isolated voltage feedback is achieved by using an
optocoupler as shown in Figure 3. Connect the collec-
tor of the optotransistor to OPTO and a pullup resistor
between OPTO and REGOUT.
Internal Regulators
As soon as power is provided to HVIN, internal power
supplies power the DCUVLO detection circuitry.
REGOUT is used to drive the internal power MOSFETs.
Bypass REGOUT to GND with a minimum 2.2µF ceram-
ic capacitor. The HVIN LDO steps down V
HVIN to a
nominal output voltage (V REGOUT ) of 8.75V. A second
parallel LDO powers REGOUT from INBIAS. A tertiary
winding connected through a diode to INBIAS powers
up REGOUT once switching commences. This powers
REGOUT to 10.5V (typ) and shuts off the current flow-
ing from HVIN to REGOUT. This results in a lower on-
chip power dissipation and higher efficiency.
V V
R
R
DCUVLOIN DCUVLO
= × +
⎛
⎝⎜ ⎞
⎠⎟
1
16
17
R C
V
f V
RCFF RCFF
IN EX
S R P P
Ч ≥
Ч Ч
−
,
( )
2
MAX5953A/MAX5953B/MAX5953C/MAX5953D
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
______________________________________________________________________________________ 17
C
+5V
R
MAX5953A
MAX5953B
MAX5953C
MAX5953D
PPWM
PGND
Figure 5. Secondary-Side Synchronous Rectifier Driver Using a
High-Speed Optocoupler