Rainbow Electronics MAX14541Е - Manual (Page 7)

3-Channel, Low-Leakage ESD Protector
MAX14541E
_______________________________________________________________________________________ 7
__________Layout Recommendations
Proper circuit-board layout is critical to suppress ESD-
induced line transients (see Figure 6). The MAX14541E
clamps to 100V; however, with improper layout, the
voltage spike at the device can be much higher. A lead
inductance of 10nH with a 45A current spike results in an
additional 450V spike on the protected line. It is essential
that the layout of the PCB follows these guidelines:
1) Minimize trace length between the connector or input
terminal, I/O_, and the protected signal line.
2) Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.
3) Ensure short low-inductance ESD transient return
paths to GND and V CC .
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
PCB.
6) Bypass V CC to GND with a low-ESR ceramic capaci-
tor as close as possible to V CC .
7) Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close as pos-
sible to the supply pin.
Figure 6. Layout Considerations
___________________________________________________Typical Application Circuit
V CC
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
PROTECTED
CIRCUIT
GND
D1
I/O_
V C
D2
L1
L3
L2
MAX14541E
0.1 µF 0.1 µF
I/0_
I/0
I/0 LINE
V
CC V
CC
PROTECTED
CIRCUIT