Rainbow Electronics MAX5153 - Manual (Page 5)

MAX5152/MAX5153
Low-Power, Dual, 13-Bit Voltage-Output DACs
with Configurable Outputs
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ELECTRICAL CHARACTERISTICS—MAX5153 (continued)
(V DD = +2.7V to +3.6V, V REFA = V REFB = 1.25V, R L = 10k
Ω
, C L = 100pF, T A = T MIN to T MAX , unless otherwise noted. Typical values
are at T A = +25°C, output buffer connected in unity-gain configuration (Figure 9).)
CS = V
DD , f DIN = 100kHz, V SCLK = 3Vp-p
(Note 4)
(Note 7)
(Note 7)
ns
Rail-to-rail (Note 6)
To 1/2LSB of full-scale, V STEP = 1.25V
40 t CL SCLK Pulse Width Low
CONDITIONS
ns 40 t CH SCLK Pulse Width High
nV-s 5 Digital Crosstalk
nV-s 5 Digital Feedthrough
µs 25
Time Required to Exit
Shutdown
µA 0 ±0.1 I FB_ Current into FBA or FBB
ns 100 t CP SCLK Clock Period
µA ±1
Reference Current in
Shutdown
µA 1 8 I DD(SHDN)
Power-Supply Current in
Shutdown
mA 0.5 0.6 I DD Power-Supply Current
V 2.7 3.6 V DD Positive Supply Voltage
ns 50 t DS DIN Setup Time
ns 0 t CHS
SCLK Rise to CS Rise Hold
Time
ns 40 t CSS
CS Fall to SCLK Rise Setup
Time
C LOAD = 200pF
V 0 to V DD Output Voltage Swing
µs 25 Output Settling Time
C LOAD = 200pF
ns 120
V/µs 0.75 SR Voltage Output Slew Rate
UNITS MIN TYP MAX SYMBOL PARAMETER
t DO2
SCLK Fall to DOUT Valid
Propagation Delay
ns 120 t DO1
SCLK Rise to DOUT Valid
Propagation Delay
ns 0 t DH DIN Hold Time
ns 100 t CSW
CS Pulse Width High
ns 40 t CS1
CS Rise to SCLK Rise Hold
ns 10 t CS0 SCLK Rise to CS Fall Delay
Note 4: SCLK minimum clock period includes rise and fall times.
Note 5: Accuracy is specified from code 40 to code 8191.
Note 6: Accuracy is better than 1LSB for V OUT greater than 6mV and less than V DD - 100mV. Guaranteed by PSRR test at the end
points.
Note 7: Digital inputs are set to either V DD or DGND, code = 0000 hex, R L = ∞ .
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS