Xilinx LogiCORE IP CAN 3.2 - Manual (Page 19)

CAN Getting Started Guide www.xilinx.com 19
UG186 April 19, 2010
Directory and File Contents
example design
The example design directory contains the example design files provided with the core.
/doc
The doc directory contains the PDF documentation provided with the core.
Table 4-3: Example Design Directory
Name Description
//example_design
_top.ucf Provides example constraints necessary for
processing the CAN core using the Xilinx
implementation tools.
_top.v[hd] The VHDL or Verilog top-level file for the
example design; it instantiates the CAN core.
.v Top-level file for the example design. Only
generated when Verilog design flow is
selected.
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Table 4-4: Doc Directory
Name Description
//doc
can_ds265.pdf CAN v3.2 Data Sheet
can_gsg186.pdf CAN v3.2 Getting Started Guide
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