Texas Instruments TAS5518 - Manual (Page 16)

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2.6 Digital Audio Interface (J60)
Digital Audio Interface (J60)
The digital audio interface contains digital audio signal data (I 2 S), clocks, etc. Please refer to the TAS5518
Data Manual for signal timing and details not covered in this document.
Table 2-8. J60 Pin Description
NET NAME
PIN
AT DESCRIPTION
NO.
SCHEMATICS
1, 3, 10,
GND Ground
12, 14, 16
Master clock input. Low-jitter system clock for PWM generation and reclocking. Ground connection
2 MCLK
from source to the TAS5518 must be a low-impedance connection.
3 GND Ground
4 SDIN1 I 2 S data 1, channel 1 and 2
5 SDIN2 I 2 S data 2, channel 3 and 4
6 SDIN3 I 2 S data 3, channel 5 and 6
7 SDIN4 I 2 S data 4, channel 7 and 8
8, 9, 15 — Reserved
11 SCLK I 2 S bit clock
13 LRCLK I 2 S left-right clock
System Interfaces 16 SLEU074 – June 2006
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