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Philips TMS320C6713 User Manual

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Application Report

SPRA921 - June 2003

1

TMS320C6713 Digital Signal Processor Optimized for High

Performance Multichannel Audio Systems

Roshan Gummattira, Philip Baltz,
Nat Seshan

DSP Applications

ABSTRACT

The TMS320C6713’s high performance CPU and rich peripheral set are tailored for
multichannel audio applications such as broadcast and recording mixing, home and large
venue audio decoders, and multi-zone audio distribution. The TMS320C6713 device is
based on the high-performance advanced VelociTI

very-long-instruction-word (VLIW)

architecture developed by Texas Instruments (TI). The VelociTI architecture provides ample
performance to decode a variety of existing digital audio formats and the flexibility to add
future formats.

This paper will describe the following parts of the TMS32C6713 processor and their impact
on high performance multichannel audio systems:

The external peripheral architecture

The C67x CPU architectural features and performance

The real-time two-level cache architecture

The multichannel audio serial ports (McASPs)

Contents

1

Introduction

2

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1.1 System I/O

2

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2

C67x CPU and Instruction Set

5

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2.1 Functional Units

5

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2.2 Fixed and Floating Point Instruction Set

5

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2.3 Load/Store Architecture

5

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2.4 Benchmark Performance

5

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3

Two-Level Cache

6

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3.1 Cache Overview

6

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3.2 Cache Hides Off-Chip Latency

6

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3.3 Unified L2 for Program and Data

7

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3.4 Real Time Features

7

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3.4.1

Interrupt Handling

7

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3.4.2

Real Time I/O

7

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3.5 Cache Summary

8

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