Datasheet – SMSC LAN9420 User Manual
Page 82
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08)
82
SMSC LAN9420/LAN9420i
DATASHEET
b. The software application must wait for all pending DMA transactions to complete. Upon completion,
no further transactions are permitted.
2. The ENERGYON event must be enabled as a PHY interrupt source. This is done by setting the
bit in the PHY’s
register.
3. The PHY must be enabled for the energy detect power down mode This is done by clearing the
bit in the PHY’s
register. Enabling the energy detect power-
down mode places the PHY in a reduced power state. In this mode of operation the PHY is not
capable of receiving or transmitting Ethernet data. In this state the PHY will assert its internal
interrupt if it detects Ethernet activity. Refer to
Section 3.6.8.2, "Energy Detect Power-Down," on
for more information.
4. Bit 0 of the Wakeup Status (WUPS[0]) in the
Power Management Control Register (PMT_CTRL)
must be cleared since a set bit will cause the immediate assertion of wake event when ED_EN is
set. The WUPS[0] bit will not clear if the internal PHY interrupt is asserted.
5. Set the
Energy-Detect Wakeup Enable (ED_EN)
Power Management Control Register
.
6. Set the
bit in the
PCI Power Management Control and Status Register
. Note that PME_EN must be set before entering the D3 state. If this bit is not set,
the internal PHY will be reset and placed in the General Power-Down state and the device will not
be able to detect an Ethernet link status change.
7. If the device is to be placed in the D3 state, set the
Power Management State (PM_STATE)
PCI Power Management Control and Status Register (PCI_PMCSR)
to 11b (‘D3’ state). The
device will enter D3
HOT
. Device behavior in this state is described in
On detection of Ethernet activity (energy), the device will assert the nPME signal. The nPME signal
will remain asserted until the
bits are
cleared by the Host.