Sun Microsystems SME5224AUPA-400 - Manual (Page 6)

6
SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache
UltraSPARC ™ -II CPU Module
July 1999 Sun Microsystems, Inc
Module ID
Module IDs are used to configure the UPA address of a module. The UPA_PORT_ID[4:3] are hardwired on
the module to “0”. UPA_PORT_ID[1:0] are brought out to the connector pins. Each module is hardwired in
the system to a fixed and unique UPA address. This feature supports systems with four or fewer processors.
For systems that need to support eight modules, UPA_SPEED[1] is connected to SYSID[2] in UDB-II to pro-
vide UPA_PORT_ID[2].
Systems which support more than eight modules must map the limited set of UPA_PORT_IDs from this mod-
ule to the range of required UPA_PORT_IDs, by implementation-specific means in the system.
System firmware (Open Boot Prom) uses UPA_CONFIG_REG[42:39] for generating correct clocks to the CPU
module and the UPA system ASICs. These bits are hardwired on the module and are known at MCAP[3:0] at
the UltraSPARC-II pins. The 4-bit MCAP value for this module is 0111b.
Module Power
Two types of power are required for this module: V
DD
at 3.3V, and V
DD_CORE
at 2.6V. The V
DD_CORE
supplies the
DC-DC regulator which in turn supplies 1.9 volts to the core of the processor chip, the UDB-II external cache
interface I/O, and the SRAM I/O. A resistor located on the module sends the program value to the power
supply so it generates V
DD_CORE
at 2.6V to the regulator.
JTAG Interface
The JTAG TCK signal is distributed to UDB-II, SRAMs and the CPU. For additional information about the
JTAG interface, see "JTAG Testability," on page 22, and "JTAG (IEEE 1149.1) Timing," on page 23.