Sun Microsystems SME5224AUPA-400 - Manual (Page 15)

15
400 MHz CPU, 4.0 MB E-Cache
UltraSPARC ™ -II CPU Module
SME5224AUPA-400
Advanced Version
July 1999 Sun Microsystems, Inc
The following table, "Propagation Delay, Output Hold Time Specifications," specifies the propagation delay
and output hold times for the UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module with a 4 Mbyte E-cache.
Timing Measurement Waveforms
t
H
Hold time
UPA_DATA [127:0] 1 0.4 – ns
UPA_ADDR [35:0]
UPA_ADDR_VALID, UPA_REQ_IN [2:0],
UPA_SC_REQ_IN, UPA_DATA_STALL,
UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L 1 0.4 – ns
UPA_ECC [15:0] 1 0.4 – ns
UPA_S_REPLY [3:0] 1 0.4 – ns
Propagation Delay, Output Hold Time Specifications
Symbol Clock-to-Out Signals and Output-Hold Signals Waveforms
400 MHz CPU
100 MHz UPA
Unit Min Max
t
P
Clock-to-
Out
UPA_DATA [127:0] 2 – 3.8 ns
UPA_ADDR [35:0]
UPA_ADDR_VALID, UPA_P_REPLY[4:0],
UPA_REQ_OUT 2 – 3.1 ns
UPA_ECC [15:0] 2 – 3.8 ns
t
OH
Output-
Hold
UPA_DATA [127:0] 2 1.1 – ns
UPA_ADDR [35:0]
UPA_ADDR_VALID, UPA_P_REPLY[4:0] 2 1.1 – ns
UPA_ECC [15:0] 2 1.1 – ns
Setup and Hold Time Specifications
Symbol Setup Signals and Hold Time Signals Waveforms
400 MHz CPU
100 MHz UPA
Unit Min Max
Figure 5. Timing Measurement Waveforms
Data Input
t
H
2.0V
2.4V
0.4V
xx_CLKx_NEG
t
SU
2.4V
1.6V
2.0V
Waveforms 1
xx_CLKx_POS
Data Input
t
H
0.8V
2.4V
0.4V
t
SU
0.8V
Rising Edge
Output
2.0V
2.4V
0.4V
xx_CLKx_NEG
t
OH
2.4V
1.6V
0.8V
Waveforms 2
xx_CLKx_POS
Falling Edge
Output
2.4V
0.4V
t
p
t
OH
t
p
0.8V
2.0V