Intel Evaluation Platform Board Manual IQ80960RM - Manual (Page 85)

IQ80960RM/RN Evaluation Board Manual C-1
PLD Code C
MODULE BATT
//TITLE SDRAM Battery Backup Enable
//PATTERN 101-1809-01
//REVISION
//AUTHOR
J. Neumann
//COMPANY Cyclone Microsystems Inc.
//DATE 10/30/97
//CHIP PALLV16V8Z-20JI
// 1/20/98 Modify target device to PALLV16V8Z-20JI
//Initial release.
PRSTn PIN 9;//Primary PCI reset
SCKE0
PIN 13; //SDRAM bank 0 clock enable
SCKE1 PIN 16; //SDRAM bank 1 clock enable
OUT0 PIN 14; //SCKE0 output enable
OUT1 PIN 17; //SCKE1 output enable
EQUATIONS
// If SDRAM clock enable goes low, SDRAM clock enable
// must be held low to ensure that the SDRAM is held in auto refresh mode.
// Reset going high will release the hold on SCKE.
OUT0 = SCKE0.PIN & PRSTn //SCKE is the set term, PRSTn is the reset term
# SCKE0.PIN & OUT0.PIN
# !SCKE0.PIN & PRSTn;
SCKE0 = 0;
SCKE0.OE = !OUT0;
//When OUT = 0, SCKE is grounded
//When OUT = 1, SCKE is high impedance
OUT1 = SCKE1.PIN & PRSTn
# SCKE1.PIN & OUT1.PIN
# !SCKE1.PIN & PRSTn;
SCKE1 = 0;
SCKE1.OE = !OUT1;
END