FUJITSU MB15C02 - Manual (Page 14)

14
MB15C02
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set
to 1.
Table.3 Divide ratio for the programmable reference divider
(5) Setting data input timing
The MB15C02 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data
bits are effective.
To set the divide ratio for the MB15C02 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t
1
(>1
µ
s): Data setup time t
2
(>1
µ
s): Data hold time t
3
(>
µ
s): Clock pulse width
t
4
(>1
µ
s): LE setup time to the rising edge of last clock t
5
(>1
µ
s): LE pulse width
Divide
ratio
(R)
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
5 1 0 1 0 0 0 0 0 0 0 0 0 0 0
6 0 1 1 0 0 0 0 0 0 0 0 0 0 0
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Data
Clock
LE
t1
t4
t5
t3 t2
Figure 5. Serial data input timing