FUJITSU SPARC ENTERPRISE SERVER M9000 - Manual (Page 41)

2-1
C H A P T E R
2
System Features
This chapter explains the following technical aspects, including features and
structures.
■ Section 2.1, “Hardware Configuration” on page 2-1
■ Section 2.2, “Partitioning” on page 2-7
■ Section 2.3, “Resource Management” on page 2-12
■ Section 2.4, “RAS” on page 2-13
2.1 Hardware Configuration
This section explains the hardware configuration, which includes the following
items:
■ CPU
■ Memory Subsystem
■ I/O Subsystem
■ System Bus
■ System Control
2.1.1 CPU
The M8000/M9000 servers use the SPARC64 VI/SPARC64 VII/SPARC64 VII+ CPU,
a proprietary high-performance multi-core processor. On-chip L2 cache memory
minimizes memory latency.
An instruction retry function has been implemented so that operation can be
continued by retrying an instruction for which an error has been detected.