Zilog Z80230 User Manual
Page 179
SCC/ESCC
User Manual
UM010903-0515
Register Descriptions
172
Bit 3: Auto Echo select bit
Setting this bit to 1 selects the Auto Echo mode of operation. In this mode, the TxD pin is con-
nected to RxD as in Local Loopback mode, but the receiver still listens to the RxD input. Trans-
mitted data is never seen inside or outside the SCC in this mode, and /CTS is ignored as a transmit
enable. This bit is reset by a channel or hardware reset.
Bit 2: DTR/Request Function select bit
This bit selects the function of the /DTR//REQ pin following the state of the DTR bit in WR5. If
this is set to 0, the /DTR//REQ pin follows the state of the DTR bit in WR5. If this bit is set to 1,
the /DTR//REQ pin goes Low whenever the transmit buffer becomes empty and in any of the syn-
chronous modes when the CRC has been sent at the end of a message. The request function on the
/DTR//REQ pin differs from the transmit request function available on the /W//REQ pin. The /
REQ does not go inactive until the internal operation satisfying the request is complete, which
occurs three to four PCLK cycles after the falling edge of /DS, /RD or /WR. If the DMA used is
edge-triggered, this difference is unimportant. The deassertion timing of the REQ mode can be
programmed to occur with the same timing as the /W/REQ pin if WR7' D4=1. This bit is reset by
a channel or hardware reset.
Bit 1: Baud Rate Generator Source select bit
This bit selects the source of the clock for the baud rate generator, If this bit is set to 0. The baud
rate generator clock comes from either the /RTxC pin or the XTAL oscillator (depending on the
state of the XTAL//no XTAL bit). If this bit is set to 1, the clock for the baud rate generator is the
SCC’s PCLK input. Hardware reset sets this bit to 0, select the /RTxC pin as the clock source for
the BRG.
Bit 0: Baud Rate Generator Enable
This bit controls the operation of the BRG. The counter in the BRG is enabled for counting when
this bit is set to 1, and counting is inhibited when this bit is set to 0. When this bit is set to 1,
change in the state of this bit is not reflected by the output of the BRG for two counts of the coun-
ter. This allows the command to be synchronized. However, when set to 0, disabling is immediate.
This bit is reset by a hardware reset.
Write Register 15 (External/Status Interrupt Control)
WR15 is the External/Status Source Control register. If the External/Status interrupts are enabled
as a group via WR1, bits in this register control which External/Status conditions cause an inter-
rupt. Only the External/Status conditions that occur after the controlling bit is set to 1 cause an
interrupt. This is true, even if an External/Status condition is pending at the time the bit is set. Bit
positions for WR15 are displayed in