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Zilog Z80230 User Manual

Page 123

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SCC/ESCC

User Manual

UM010903-0515

Data Communication Modes

116

Only the CRC-CCITT polynomial is used in SDLC mode. This is selected by setting bit D2 in

WR5 to 0. This bit controls the selection for both the transmitter and receiver. The initial state of

the generator and checker is controlled by bit D7 of WR10. When this bit is set to 1, both the gen-

erator and checker have an initial value of all 1s, and if this bit is set to 0, the initial values are all

0s.

The SCC does not automatically preset the CRC generator, so this is done in software. This is

accomplished by issuing the Reset Tx CRC command, which is encoded in bits D7 and D6 of

WR0. For proper results, this command is issued while the transmitter is enabled and idling. If the

CRC is to be used, the transmit CRC generator is enabled by setting bit D0 of WR5 to 1. The CRC

is normally calculated on all characters between opening and closing flags, so this bit is usually set

to 1 at initialization and never changed. On the 85X30 with Auto EOM Latch reset mode enabled

(WR7' bit D1=1), resetting of the CRC generator is done automatically.

Enabling the CRC generator is not sufficient to control the transmission of the CRC. In the SCC,

this function is controlled by Tx Underrun/EOM bit, which may be reset by the processor and set

by SCC. On the 85X30 with Auto EOM Reset mode enabled (WR7' bit D1=1), resetting of the Tx

Underrun/EOM Latch is done automatically.

Ordinarily, a frame is terminated with a CRC and a flag, but the SCC may be programmed to send

an abort and a flag in place of the CRC. This option allows the SCC to abort a frame transmission

in progress if the transmitter is accidentally allowed to underrun. This is controlled by the Abort/

Flag on Underrun bit (D2) in WR10. When this bit is set to 1, the transmitter will send an abort

and a flag in place of the CRC when an underrun occurs. The frame is terminated normally with a

CRC and a flag if this bit is 0.

The SCC is also able to send an abort by a command from the processor. When the Send Abort

command is issued in WR0, the transmitter sends eight consecutive 1s and then idles. Since up to

five consecutive 1s may be sent prior to the command being issued, a Send Abort causes a

sequence of from eight to thirteen 1s to be transmitted. The Send Abort command also clears the

transmit data FIFO.

When transmitting in SDLC mode, note that all data passes through the zero inserter, which adds

an extra five bit times of delay between the Transmit Shift register and the TxD Pin.

When the transmitter underruns (both the Transmit FIFO and Transmit Shift register are empty),

the state of the Tx Underrun/EOM bit determines the action taken by the SCC.

If the Tx Underrun/EOM bit is set to 1 when the underrun occurs, the transmitter sends flags with-

out sending the CRC. If this bit is reset to 0 when the underrun occurs, the transmitter sends either

the accumulated CRC followed by flags, or an abort followed by flags, depending on the state of

the Abort/Flag on the Underrun bit in the WR10, bit D1. A summary is listed in

Table

.

The Reset Tx Underrun/EOM Latch command is encoded in bits D7 and D6 of WR0.

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