Zilog Z80230 - Manual (Page 102)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
95
The SCC may be programmed to accept a transmit clock that is one, sixteen, thirty-two, or sixty-
four times the data rate. This is selected by bits D7 and D6 in WR4, in common with the clock fac-
tor for the receiver.
When using Isosynchronous (X1 clock) mode, one-and-a-half stop bits are not allowed.
Only one or two stop bits should be selected. If some length other than one stop bit is
desired in the times one mode, only two stop bits may be used. Also, in this mode, the
Transmitter usually needs to send clocking information (transmit clock) along with the data
in order to receive data correctly.
There are two modem control signals associated with the transmitter provided by the SCC; /RTS
and /CTS.
The /RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5, unless
the Auto Enables mode bit (D5) is set in WR3. When Auto Enables is set, the /RTS pin immedi-
ately goes Low when the RTS bit is set. However, when the RTS bit is reset, the /RTS pin remains
Low until the transmitter is completely empty and the last stop bit has left the TxD pin. Thus, the /
RTS pin may be used to disable external drivers for the transmit data. The /CTS pin is ordinarily a
simple input to the CTS bit in RR0. However, if Auto Enables mode is selected, this pin becomes
an enable for the transmitter. That is, if Auto Enables is on and the /CTS pin is High, the transmit-
ter is disabled; the transmitter is enabled while the /CTS pin is Low.
The initialization sequence for the transmitter in Asynchronous mode is WR4 first to select the
mode, then WR3 and WR5 to select the various options. At this point the other registers should be
initialized as necessary. When all of this is complete, the transmitter may be enabled by setting bit
D3 of WR5 to 1. Note that the transmitter and receiver may be initialized at the same time.
Asynchronous transmit on the NMOS/CMOS
On the NMOS/CMOS version of the SCC, characters are loaded from the transmit buffer to the
shift register where they are given a start bit and a parity bit (as programmed), and are shifted out
to the TxD pin. The transmit buffer empty interrupt and the DMA request (either /W//REQ or /
DTR//REQ pin) are asserted when the transmit buffer is empty, if these are enabled. At this time,
the CPU or the DMA is able to write one byte of transmit data. The Transmit Buffer Empty (TBE)
bit (RR0, bit D2) also follows the state of the transmit buffer. The All Sent bit, RR1, bit D0, can be
polled to determine when the last bit of transmit data has cleared the TxD pin. For details about the
transmit DMA and transmit interrupts, see Transmit Interrupts and Transmit Buffer Empty Bit on
page 49.
Asynchronous transmit on the ESCC
On the ESCC, characters are loaded from the Transmit FIFO to the shift register where they are
given a start bit and a parity bit (as programmed), and are shifted out to the TxD pin. The ESCC
can generate an interrupt or DMA request depending on the status of the Transmit FIFO. If WR7'
D5 is reset, the transmit buffer empty interrupt and DMA request (either /W//REQ or /DTR//REQ
pin) are asserted when the entry location of the Transmit FIFO is empty (one byte can be written).
If WR7' D5 is set, the transmit interrupt and DMA request is generated when the Transmit FIFO is
completely empty (four bytes can be written). The Transmit Buffer Empty (TBE) bit in RR0, bit
Note: