Zilog Z16C30 - Manual (Page 24)

1-11
Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
Serial Clock
Logic
DPLL
Counters
BRG0, BRG1
Transmitter
Interrupt
Control
Interrupt
Control
Bus
Interface
Receive
FIFO
Receive
FIFO
Receiver
Receiver
Transmit
FIFO
DPLL
Counters
BRG0, BRG1
Serial Clock
Logic
Transmitter
Transmit
FIFO
Channel A
Channel B
16-Bit Internal
Data Bus
DMA
Controller,
System
Memory
Host
Processor
Figure 1-3. USC ® Block Diagram
UM009402-0201