Zilog Z16C30 - Manual (Page 163)

8-8
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
8.7 TEST MODES (Continued)
D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
0
TxC Pad
Rx Sync
/Rx Clock
BRG0 Output
CTR0 Output
Tx Byte Clock
DPLL TxC Output
0
0
Rx Byte Clock
Tx Complete
BRG1 Output
CTR1 Output
RxC Pad
DPLL RxC Output
Figure 8-2. Test Mode Data Register with TMCR 4-0=00111 (Clock Mux Inputs)
UM009402-0201