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Ez80f92, Ez80=iic-bus-master – Zilog eZ80F92 User Manual

Page 70

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UM013911-0607

Schematic Diagrams

eZ80F92 Development Kit

User Manual

66

Figure 23. Schematic Diagram, #2 of 9—100-Pin QFP eZ80F92 Device

=

=
=

=

eZ80=IIC-bus-master

GoldCap

(= JTAG0)

PLACE CAPS CLOSE
TO PINS
97,7,33,43

D[0..7]

A[0..23]

CLK_OUT

XOUT

XIN

CLK_OUT

XOU

T

VDD

-RESET

VSS

XIN

D0 D1

D2 D3

D4 D5 D6

D7

A0

A1
A2

A3

A4
A5

A6

A7
A8

A9
A10

A11

A12
A13

A14

A15
A16

A17
A18

A19

A20

A21

A22 A23

-CS0 -CS1 -CS2

-CS3

-CS[0..3]

D[0..7]

PB

7

PB

6

PB

5

PB

4

PB

3

PB

2

PB

1

PB

0

PC7

PC6 PC5 PC4

PC3 PC2

PC1 PC0

PC[0..7]

PB[0..7]

IICSCL

IICSDA

-NMI

PD7

PD6
PD5

PD4

PD3
PD2

PD1
PD0

TDO
TDI

JTAG1

TRIGOUT

JTAG2

TCK

JTAG3

TMS

JTAG4

RTC_VDD

RTC_XOUT
RTC_XIN

PD[0..7]

JTAG[1..4]

-BUSREQ

-BUSACK

-HALT_SLP

-IORE

Q

-MR

EQ

-RD -WR

-INST

RD

-W

AIT

IICSDA

IICSCL

PB[0..7]

PC[0..7]

PD[0..7]

A[0..23]

-CS[0..3]

-RESET

-IOREQ

-MREQ

-RD

-WR

-INSTRD

-WAIT

-HALT_SLP

-BUSACK

-BUSREQ

-NMI

JTAG[1..4]

RTC_XOUT

RTC_XIN

RTC_VDD

RTC_VDD

TDO

V3.3

GND

V3.3

V3.3

V3.3

V3.3

C18
100nF

R29

10k

C21
1nF

R37

0

R32

220

R31 0

D1
TMM BAT 41

MINIMELF_AK

R28
100

C19
0,1F

GOLDCAP_SD

C22
1nF

C24

18pF

U8

eZ80F92

TQFP100

83

75

87

82

84

86

96

97

100

35

85

74

17

54

66

73

99

49

98

20

81

64

88

89

90

91

92

93

94

95

80

72

79

65

78

29

77

45

76

30

63

71

50

62

53

70

60

36

69

21

68

59

67

31

55

58

7

37

33

61

46

1

51

22

56

57

26

34

27

32

28

52

38

48

2

8

39

47

40

3

23

4

43

41

5

24

42

44

6

9

25

10

18

11
12

13

19

14
15

16

PC7/RI1

PD7/RI0

VDD

PC6/DCD1

VSS

XOUT

VDD

VSS

PHI

D0

XIN

PD6/DCD0

A14

BUSACK

TDO

PD5/DSR0

SCL

INSTRD

SDA

A15

PC5/DSR1

TRIGOUT

PB0/T0_IN

PB1/T1_IN

PB2/SS

PB3/SCK

PB4/T4_OUT

PB5/T5_OUT

PB6/MISO

PB7/MOSI

PC4/DTR1

PD4/DTR0

PC3/CTS1

TDI (ZDA)

PC2/RTS1

CS0

PC1/RxD1

IOREQ

PC0/TxD1

CS1

TCK (ZCL)

PD3/CTS0

WAIT

TMS

BUSREQ

PD2/RTS0/IR_SD

RTC_VDD

D1

PD1/RxD0/IR_RXD

A16

PD0/TxD0/IR_TXD

RTC_XOUT

VDD

CS2

HALT_SLP

RTC_XIN

VDD

D2

VDD

VSS

MREQ

A0

RESET

A17

VDD

VSS

A21

VSS

A22

CS3

A23

NMI

D3

WR

A1

VSS

D4

RD

D5

A2

A18

A3

VDD

D6

A4

A19

D7

VSS

A5

A6

A20

A7

VDD

A8
A9

A10

VSS

A11
A12

A13

Y3
32.768kHz
XTAL3

Y2

20 MHz

HC49SM

R27

100K

C23
1nF

C16
20pF

C17
20pF

C20

18pF

D[0..7]

A[0..23]

IICSCL

IICSDA

CLK_OUT

PB[0..7]

PC[0..7]

PD[0..7]

-CS[0..3]

-RESET

-IOREQ

-MREQ

-RD

-WR

-INSTRD

-HALT_SLP

-BUSACK

-WAIT

-BUSREQ

-NMI

JTAG[1..4]

RTC_VDD

TDO