MUTEC MC-3.2 Smart Clock HD - Manual (Page 18)

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Manual SDs-01 D 3.2.2003 17:45 Uhr Seite 16
18
WCLK multiplier 5
For the AES/EBU output pair are 3 multiply functions available:
x 1, x 2, x 4
Due to the maximum possible AES/EBU clock frequency of 192.0kHz, the
functions of these multipliers are dependent on the adjusted basis clock.
Example 1
The basis clock runs at 32.0kHz, 44.1kHz or 48.0kHz:
x 1: AES/EBU outputs run at 32.0kHz, 44.1kHz or 48.0kHz
x 2: AES/EBU outputs run at 64.0kHz, 88.2kHz or 96.0kHz
x 4: AES/EBU outputs run at 128.0kHz, 176.4kHz or 192.0kHz
Example 2
The basis clock runs at 88.2kHz or 96.0kHz:
x 1: AES/EBU outputs run at 88.2kHz or 96.0kHz
x 2: AES/EBU outputs run at 176.4kHz or 192.0kHz
x 4: AES/EBU outputs run at 176.4kHz or 192.0kHz
Example 3
The basis clock runs at 176.4kHz or 192.0kHz:
x 1: AES/EBU outputs run at 176.4kHz or 192.0kHz
x 2: AES/EBU outputs run at 176.4kHz or 192.0kHz
x 4: AES/EBU outputs run at 176.4kHz or 192.0kHz
The factory default is set at x 1.
WCLK multiplier 6
Both S/PDIF outputs, optical and coaxial, receive same clock rate settings.
For the S/PDIF output pair are 3 multiply functions available:
x 1, x 2, x 4
Due to the maximum possible S/PDIF clock frequency of 192.0kHz, the
functions of these multipliers are dependent on the adjusted basis clock.
Example 1
The basis clock runs at 32.0kHz, 44.1kHz or 48.0kHz:
x 1: S/PDIF outputs run at 32.0kHz, 44.1kHz or 48.0kHz
x 2: S/PDIF outputs run at 64.0kHz, 88.2kHz or 96.0kHz
x 4: S/PDIF outputs run at 128.0kHz, 176.4kHz or 192.0kHz
Example 2
The basis clock runs at 88.2kHz or 96.0kHz:
x 1: S/PDIF outputs run at 88.2kHz or 96.0kHz
x 2: S/PDIF outputs run at 176.4kHz or 192.0kHz
x 4: S/PDIF outputs run at 176.4kHz or 192.0kHz
Example 3
The basis clock runs at 176.4kHz or 192.0kHz:
x 1: S/PDIF outputs run at 176.4kHz or 192.0kHz
x 2: S/PDIF outputs run at 176.4kHz or 192.0kHz
x 4: S/PDIF outputs run at 176.4kHz or 192.0kHz
The factory default is set at x 1.