IBM X3950 M2 - Manual (Page 4)

Combining high-performance architecture with high-performance Xeon processors
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twice as many FSBs as before and each is 60% faster than before.
Intel Extended Memory 64 Technology (EM64T) 64-bit extensions allow the Xeon processor
to use large memory addressing when running with a 64-bit operating system. This in turn lets
individual software processes directly access more than 4GB of RAM, which was the limit of 32-
bit addressing. This can result in much higher performance for certain kinds of programs, such
as database management and CAD. Additional registers and instructions (SSE3) can further
boost performance for applications written to use them. Customers should contact their software
provider to determine their software support for EM64T.
Intel’s Virtualization Technology (VT) integrates hardware-level virtualization hooks that allow
operating system vendors to better utilize the hardware for virtualization workloads, a key
workload for the eX4 platform.
eX4 Chipset ‘Snoop’ Filtering
One of the core features of the eX4 chipset that gives the platform a performance advantage is
the snoop filter. The Xeon Coherency Protocol or “snoop” is an operation that occurs whenever
a processor in an SMP system needs to update a memory address during normal operation.
The snoop occurs when the processor getting ready to operate on a piece of data asks the other
processors in the SMP complex to verify they have not modified the same piece of data without
writing back from their cache. This operation increases traffic on the front side bus.
The eX4 chipset contains 324MB of EDRAM within the Northbridge chip. This copies all data as
it is written to the processor cache, allowing the chipset to respond directly to the snoop
requests. This reduces the overall traffic across the FSB and helps to improve system
performance over other architectures. (Intel now offers a first-generation snoop filter in their
7300 chipset; however it contains only 64MB of RAM which is 80% smaller than the eX4 fourth-
generation solution.)
Advanced Buffer eXecution
The IBM Advanced Buffer
eXecution (ABX) chips (2 per
chassis) provide the x3850 M2 /
3950 M2’s DDR2 memory with
up to 60% more bandwidth than
other vendors can manage using
more expensive (and more
energy-hungry) Fully Buffered
DIMMs (FB-DIMMs). The ABX
chip uses two buffers per
memory card to re-drive the
signals from the eX4 memory
controller to the DIMMs,
bypassing the latency-adding
buffers used on each FB-DIMM.
The use of ABX reduces
latency by 20% vs. FB-DIMMs.
This feature is a unique IBM
enhancement, not offered by
other x86 server architectures
(using either Intel or AMD processors).
XceL4v Dynamic Server Cache
Another performance feature of the eX4 chipset is the XceL4v L4 cache. When using a single
node (chassis), the cache works with the snoop filter to help reduce FSB traffic. When more
than one node is used, 256MB of virtual cache per node (taken from main memory) is used for
interprocessor communications between chassis, to keep data in synch. In a 4chassis
configuration, this amounts to as much as 1GB of L4 cache. This not only compensates for any
performance hit that might otherwise result from sending data across the distances between
processors in multiple chassis, it actually results in a performance improvement versus a single
chassis. (IBM X3 and eX4 servers have achieved well over 100 #1 results on industry-standard
benchmarks, such as TPC-C, TPC-E, TPC-H, SAP SD, vConsolidate, Vmark, and more.)
This feature is a unique IBM enhancement, not offered by other x86 server architectures (using
either Intel or AMD processors).
Scalable Virtual L4
cache
IB: 2 x12
533
MT/s
1066 MT/s
2.5 GT/s
SP: 3 x8
2.1
GT/s
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