Intel 80L186EA - Manual (Page 29)

80C186EA 80C188EA 80L186EA 80L188EA
AC SPECIFICATIONS (Continued)
Relative Timings (80C186EA25 20 13 80L186EA13 8)
Symbol Parameter Min Max Unit Notes
RELATIVE TIMINGS
T
LHLL
ALE Rising to ALE Falling T b 15 ns
T
AVLL
Address Valid to ALE Falling T b 10 ns
T
PLLL
Chip Selects Valid to ALE Falling T b 10 ns 1
T
LLAX
Address Hold from ALE Falling T b 10 ns
T
LLWL
ALE Falling to WR Falling T b 15 ns 1
T
LLRL
ALE Falling to RD Falling T b 15 ns 1
T
RHLH
RD Rising to ALE Rising T b 10 ns 1
T
WHLH
WR Rising to ALE Rising T b 10 ns 1
T
AFRL
Address Float to RD Falling 0 ns
T
RLRH
RD Falling to RD Rising (2 T) b 5 ns 2
T
WLWH
WR Falling to WR Rising (2 T) b 5 ns 2
T
RHAV
RD Rising to Address Active T b 15 ns
T
WHDX
Output Data Hold after WR Rising T b 15 ns
T
WHDEX
WR Rising to DEN Rising T b 10 ns 1
T
WHPH
WR Rising to Chip Select Rising T b 10 ns 1 4
T
RHPH
RD Rising to Chip Select Rising T b 10 ns 1 4
T
PHPL
CS Inactive to CS Active T b 10 ns 1
T
DXDL
DEN Inactive to DT R Low 0 ns 5
T
OVRH
ONCE (UCS LCS) Active to RESIN Rising T ns 3
T
RHOX
ONCE (UCS LCS) to RESIN Rising T ns 3
NOTES
1 Assumes equal loading on both pins
2 Can be extended using wait states
3 Not tested
4 Not applicable to latched A2 1 These signals change only on falling T
1
5 For write cycle followed by read cycle
6 Operating conditions for 25 MHz are 0 C to a70 C V
CC e 5 0V g 10%
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