Motorola DSP56301 User Manual

Page 370

Index

-14

DSP56301 User’s Manual

Zero (Z) 4-11

Extended Mode Register (EMR) 4-7

Arithmetic Saturation Mode (SM) 4-7
Cache Enable (CE) 4-8
Core Priority (CP) 4-7
DO FOREVER (FV) Flag 4-8
Instruction Cache Enable (CE) 4-7
Rounding Mode (RM) 4-7
Sixteen-bit Arithmetic Mode (SA) 4-8

Mode Register (MR) 4-7

Do Loop Flag (LF) 4-8
Double-Precision Multiply Mode (DM) 4-9
Interrupt Mask (I) 4-10
Scaling (S) Mode 4-10
Sixteen-bit Compatibility (SC) Mode 4-9

programming sheet B-13

Status/Command Configuration Register

(CSTR/CCMR) 6-64
Data Parity Reported (DPR) 6-65
Detected Parity Error (DPE) 6-65
DEVSEL Timing (DST[1–0]) 6-65
Fast Back-to-Back Capable (FBBC) 6-66
Parity Error Response (PERR) 6-66
PCI Bus Master Enable (BM) 6-66
PCI Memory Space Enable (MSE) 6-66
Received Master Abort (RMA) 6-65
Received Target Abort (RTA) 6-65
Signaled System Error (SSE) 6-65
Signalled Target Abort (STA) 6-65
System Error Enable (SERE) 6-66
Wait Cycle Control (WCC) 6-66

Stop Delay Mode (SD) bit 4-15
STOP instruction 6-12

8-6

STOP reset 6-12
Switch mode 1-5
switching memory configuration dynamically 3-5
switching memory sizes 3-2
Synchronous mode 7-10

Synchronous Serial Interface Status Register

(SSISR) 7-14

7-28

Receive Data Register Full (RDF) 7-28
Receiver Frame Sync Flag (RFS) 7-29
Receiver Overrun Error Flag (ROE) 7-28
Serial Input Flag 0 (IF0) 7-29
Serial Input Flag 1 (IF1) 7-29
Transmit Data Register Empty (TDE) 7-28
Transmit Frame Sync Flag (TFS) 7-29
Transmitter Underrun Error Flag (TUE) 7-28

Synchronous/Asynchronous (SYN) bit 7-21
System Error Enable (SERE) bit 6-66
system initialization 5-1
SZ register 1-8

TA Synchronize Select (TAS) bit 4-14
Target Wait State Disable (TWSD) bit 6-49
Test Access Port (TAP) 1-5

1-9

signals 2-29

Test Clock (TCK) 2-29
Test Data Input (TDI) 2-29
Test Data Output (TDO) 2-29
Test Mode Select (TMS) 2-29
Test Reset (

TRST

2-29

Time Slot Register (TSR) 7-33
timer 2-2

2-27

after Reset 9-3
enabling 9-4
exception 9-4

Compare 9-4
Overflow 9-4

GPIO 5-7
initialization 9-3
operating modes 9-5

Capture (mode 6) 9-5

9-14

9-18

Event Counter (mode 3) 9-5

9-12

GPIO (mode 0) 9-5

9-6

Input Period (mode 5) 9-5

9-14

9-16

Input Width (mode 4) 9-5

9-14

overview 9-6
Pulse (mode 1) 9-5

9-8

Pulse Width Modulation (PWM) (mode 7) 9-5

9-14

9-19

reserved 9-25
setting 9-4
signal measurement modes 9-14
Toggle (mode 2) 9-5

9-10

watchdog modes 9-21

Watchdog Pulse (mode 9) 9-5

9-22

Watchdog Toggle (mode 10) 9-5

9-22

prescaler counter 9-25
programming model 9-25
signals 2-1
special cases 9-25
timer compare interrupts 9-32
Timer Compare Register (TCPR) 9-34
Timer Control/Status Register (TCSR) 9-28

Data Input (DI) 9-29
Data Output (DO) 9-29
Direction (DIR) 9-30
Inverter (INV) 9-30

9-32

Prescaler Clock Enable (PCE) 9-29
Timer Compare Flag (TCF) 9-29
Timer Compare Interrupt Enable (TCIE) 9-32
Timer Control (TC) 9-31
Timer Enable (TE) 9-32
Timer Overflow Flag (TOF) 9-29