Sundance SMT8121 - Manual (Page 18)

Figure 10: control panel of the SMT381
Clock source: the SMT391 provides three clock sources for the sampling clock of
the ADC. This drop-down list allows selecting which one to use.
Sampling rate: select the sampling frequency of the DAC.
Note: the clock source must be set to “External RF” when the clock of the SMT391
is used as the sampling clock for the SMT381 via connector J5.
8.1.3 Stand alone mode
“com.sundance.example.smt8121.sa” is a stand alone version of the application.
The application doesn’t interact with the host PC. There is no display of the FFT
and the parameters of the application are hard-coded in the DSP source code.
8.2 Implementation
The example is developed with 3L Diamond.
Source code for the example is provided.
The diagram shows the main tasks used in the application. The tasks in yellow run
on the DSP of the SMT395; the tasks in red run on the FPGA of the SMT368/391;
the tasks in blue run on the FPGA of the SMT368A/381.
To keep the diagram clear only the tasks playing a major role in the application are
shown. The functionality and use of the tasks which don’t appear can usually be
deduced from their name and connection in the application.
Application Note SMT8121 Page 18 of 26 Last Edited: 19/02/2009 16:32:00