Sundance SMT8091-395VP - Manual (Page 11)

Version 1.0 Page 11 of 12 SMT80901_395VP20 User Manual
Description of the functions in the test software menu
The 3L application provided with the system allows the two options. The first one
allows to configure the SMT391-VP by using the SMT395VP via comport and next do
the data acquisition on both channels I and Q at several sampling frequencies. The
second option skips the configuration of the FPGA of the SMT391VP and then do the
data acquisition as defined previously.
“ '0' to configure the FPGA and acquire data”
This command loads the SMT391 bitstream contained in the directory where the
application is running from as well as the Start and End.
The ConfigStdioCP() function used is provided with the SMT6500 package. Please
refer to the
SMT6500 for more details. This function loads the SMT391 firmware in
the FPGA via comport. Once the FPGA is configured, it starts to set up the ADC and
then acquire the input signals at several frequencies.
Both channels I and Q are captured and the acquisition starts with a sampling
frequency from 50MHz to 1000MHz by step of 50MHz. For the frequencies below
600MHz the clock synthesizer generates the sampling frequencies. Above 600MHz
the VCO generates them.
“ '1' to skip the configuration of the FPGA and acquire data”
This command skips the SMT391 configuration and should be use only when the
FPGA is already configured. This option starts to configure the ADC and then acquire
the input signals at several frequencies (as explained in the section just above).
CPLDReset(): Pulse on Config Line - for FPGA reconfiguring
By toggling the Config line, it is possible to reload the FPGA with a different
bitstream.
Configuring internal Registers
Set up the internal registers with values defines at the beginning of the application.
Capturing data
This command captures data from both I and Q channels, one after the other (not
simultaneously). Data are then stored into two separate files into the directory where
the application has been started. Files are called ChannelA_frequency.txt and
ChannelB_frequency.txt.
Note that without configuring the FPGA followed by its internal registers, none of the
other options will work.